Ashok V. Krishnamoorthy,1
Philippe J. Marchand,2
Gökçe Yayla,2
and Sadik C. Esener2
1Advanced Photonic Research Department, AT&T Bell Laboratories, Room 4B-523, 101 Crawfords Corner Road, Holmdel, New Jersey 07733.
2The other authors are with the Department of Electrical and Computer Engineering, University of California, San Diego, La Jolla, California 92093-0407.
Ashok V. Krishnamoorthy, Philippe J. Marchand, Gökçe Yayla, and Sadik C. Esener, "Photonic content-addressable memory system that uses a
parallel-readout optical disk," Appl. Opt. 34, 7621-7638 (1995)
We describe a high-performance associative-memory system that can be implemented
by means of an optical disk modified for parallel readout and a custom-designed
silicon integrated circuit with parallel optical input. The system can achieve
associative recall on 128 × 128 bit images and also on variable-size
subimages. The system’s behavior and performance are evaluated on the
basis of experimental results on a motionless-head parallel-readout optical-disk
system, logic simulations of the very-large-scale integrated chip, and a
software emulation of the overall system.
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Standard Cell Delay Times as Obtained from the MOSIS Servicea
Level and Delay Variable
Formula for Delay Calculation
Level 1 (leaf unit)
tinv
[0.37 +
(0.65CL)]
ns
tXNOR
[0.7 +
(1.06CL)]
ns
Level 2 (half-adder)
tAND
[0.67 +
(0.8CL)]
ns
tXOR
[0.67 +
(1.06CL)]
ns
Level 3 (2-bit adder)
tFAS
(sum bit)
[2.51 +
(0.65CL)]
ns
tFAC
(carry bit)
[1.21 +
(0.55CL)]
ns
Level L (root
unit comparator)
tcomp
tNOR{log[2
log(N + 1)] +
1}
tNOR
[0.38 +
(0.57CL)]
ns
See Ref. 34. In these
calculations, CL is the
input capacitance of following stage, Lint
is interconnection length in micrometers, and
Cint and
Rint are the interconnection capacitance
and resistance, respectively, per unit length
Rint including the resistance of
contacts. Rint = [468 × 0.0375
Lint] Ω;
Cint =
[0.2Lint]fF.
Tables (5)
Table 1
Critical Parameters for a Parallel-Access Optical Disk
Standard Cell Delay Times as Obtained from the MOSIS Servicea
Level and Delay Variable
Formula for Delay Calculation
Level 1 (leaf unit)
tinv
[0.37 +
(0.65CL)]
ns
tXNOR
[0.7 +
(1.06CL)]
ns
Level 2 (half-adder)
tAND
[0.67 +
(0.8CL)]
ns
tXOR
[0.67 +
(1.06CL)]
ns
Level 3 (2-bit adder)
tFAS
(sum bit)
[2.51 +
(0.65CL)]
ns
tFAC
(carry bit)
[1.21 +
(0.55CL)]
ns
Level L (root
unit comparator)
tcomp
tNOR{log[2
log(N + 1)] +
1}
tNOR
[0.38 +
(0.57CL)]
ns
See Ref. 34. In these
calculations, CL is the
input capacitance of following stage, Lint
is interconnection length in micrometers, and
Cint and
Rint are the interconnection capacitance
and resistance, respectively, per unit length
Rint including the resistance of
contacts. Rint = [468 × 0.0375
Lint] Ω;
Cint =
[0.2Lint]fF.