Abstract
Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.
© 2003 Optical Society of America
Full Article | PDF ArticleMore Like This
Frederic Lacroix, Eric Bernier, Michael H. Ayliffe, Frank A. P. Tooley, David V. Plant, and Andrew G. Kirk
Appl. Opt. 41(8) 1541-1555 (2002)
Toshikazu Sakano, Takao Matsumoto, and Kazuhiro Noguchi
Appl. Opt. 34(11) 1815-1822 (1995)
Yongsheng Liu, Brian Robertson, Guillaume C. Boisset, Michael H. Ayliffe, Rajiv Iyer, and David V. Plant
Appl. Opt. 37(14) 2895-2914 (1998)