Abstract
IC technologies and major equalizer structures were discussed for designing a 40Gb/s equalizer chip. Insights, suggestions or comments were given on designing all building blocks for an equalizer circuit, design methodology, and packaging the die.
© 2006 Optical Society of America
PDF ArticleMore Like This
Hong Jiang, Ross Saunders, and Stephen Colaco
OWO2 Optical Fiber Communication Conference (OFC) 2005
M. Nakamura, H. Nosaka, M. Ida, K. Kurishima, and M. Tokumitsu
TuG4 Optical Fiber Communication Conference (OFC) 2004
M. Nakamura, K. Murata, and M. Tokumitsu
OThN6 Optical Fiber Communication Conference (OFC) 2007