OSA's Digital Library

Applied Optics

Applied Optics


  • Vol. 37, Iss. 2 — Jan. 10, 1998
  • pp: 233–253

Optimal usage of available wiring resources in diffractive–reflective optoelectronic multichip modules

José L. Cruz-Rivera, D. Scott Wills, Thomas K. Gaylord, and Elias N. Glytsis  »View Author Affiliations

Applied Optics, Vol. 37, Issue 2, pp. 233-253 (1998)

View Full Text Article

Enhanced HTML    Acrobat PDF (1344 KB)

Browse Journals / Lookup Meetings

Browse by Journal and Year


Lookup Conference Papers

Close Browse Journals / Lookup Meetings

Article Tools



Advances in VLSI and optoelectronic multichip module technologies are enabling the construction of ultracompact massively parallel processing systems. The technological parameters that define the wirability and delay characteristics of these technologies have a significant impact on the system architecture. An analytical model is presented that allows the design space exploration of the interconnection networks associated with multinode chips packaged on a single multichip module substrate. Possible system designs are evaluated for a two-level interconnect with separate k-ary n-cube networks for interchip and intrachip communication. The impact of several architectural and technological parameters on the optimal network implementation (based on average no-load latency) is analyzed.

© 1998 Optical Society of America

OCIS Codes
(050.1970) Diffraction and gratings : Diffractive optics
(200.4650) Optics in computing : Optical interconnects
(250.0250) Optoelectronics : Optoelectronics

Original Manuscript: April 9, 1997
Revised Manuscript: September 2, 1997
Published: January 10, 1998

José L. Cruz-Rivera, D. Scott Wills, Thomas K. Gaylord, and Elias N. Glytsis, "Optimal usage of available wiring resources in diffractive–reflective optoelectronic multichip modules," Appl. Opt. 37, 233-253 (1998)

Sort:  Author  |  Year  |  Journal  |  Reset  


  1. “National technology roadmap for semiconductors,” Tech. Rep., Semiconductor Industry Association, San José, Calif. (1994).
  2. R. R. Tummala, “Multichip packaging—a tutorial,” Proc. IEEE 80, 1924–1941 (1992). [CrossRef]
  3. M. R. Feldman, S. C. Esener, C. C. Guest, S. H. Lee, “Comparison between optical and electrical interconnects based on power and speed considerations,” Appl. Opt. 27, 1742–1751 (1988). [CrossRef] [PubMed]
  4. M. R. Feldman, C. C. Guest, “Interconnect density capabilities of computer generated holograms for optical interconnections of VLSI circuits,” Appl. Opt. 28, 3134–3137 (1989). [CrossRef] [PubMed]
  5. M. R. Feldman, C. C. Guest, T. J. Drabik, S. C. Esener, “Comparison between electrical and free-space optical interconnections for fine-grain processor arrays based on interconnect density capabilities,” Appl. Opt. 28, 3820–3829 (1989). [CrossRef] [PubMed]
  6. M. R. Feldman, C. C. Guest, “Holograms for optical interconnects for very large scale integrated circuits fabricated by electron-beam lithography,” Opt. Eng. 28, 915–921 (1989). [CrossRef]
  7. K. H. Brenner, F. Sauer, “Diffractive–reflective optical interconnects,” Appl. Opt. 27, 4251–4254 (1988). [CrossRef] [PubMed]
  8. S. K. Patra, J. Ma, V. H. Ozguz, S. H. Lee, “Alignment issues in packaging for free-space optical interconnects,” Opt. Eng. 33, 1561–1570 (1994). [CrossRef]
  9. J. Fan, B. Catanzaro, V. H. Ozguz, C. K. Cheng, S. H. Lee, “Design considerations and algorithms for partitioning opto-electronic multichip modules,” Appl. Opt. 34, 3116–3127 (1995). [CrossRef] [PubMed]
  10. J. Fan, B. Catanzaro, F. Kiamilev, S. C. Esener, S. H. Lee, “Architecture of an integrated computer-aided design system for optoelectronics,” Opt. Eng. 33, 1571–1580 (1994). [CrossRef]
  11. L. J. Camp, R. Sharma, M. R. Feldman, “Guided-wave and free-space optical interconnects for parallel-processing systems: a comparison,” Appl. Opt. 33, 6168–6180 (1994). [CrossRef] [PubMed]
  12. W. J. Dally, “Performance analysis of k-ary n-cube interconnection networks,” IEEE Trans. Comput. 39, 775–785 (1990). [CrossRef]
  13. A. Agarwal, “Limits on interconnection network performance,” IEEE Trans. Parallel Distribut. Syst. 2, 398–412 (1991). [CrossRef]
  14. S. Abraham, K. Padmanabhan, “Performance of multicomputer networks under pin-out constraints,” J. Parallel Distribut. Comput. 12, 237–248 (1991). [CrossRef]
  15. S. L. Scott, J. R. Goodman, “The impact of pipelined channels on k-ary n-cube networks,” IEEE Trans. Parallel Distribut. Syst. 5, 2–16 (1994). [CrossRef]
  16. D. Basak, D. K. Panda, “Designing clustered multiprocessor systems under packaging and technological advancements,” IEEE Trans. Parallel Distribut. Syst. 7, 962–978 (1996). [CrossRef]
  17. M. Raksapatcharawong, T. M. Pinkston, “An optical interconnect model for k-ary n-cube wormhole networks,” in Proceedings of the Tenth International Parallel Processing Symposium (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 666–672.
  18. J. L. Cruz-Rivera, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Architectural desin issues for optoelectronic k-ary n-cube interconnection networks,” presented at the 1995 Optical Society of America Annual Meeting, Portland, Oregon, 10–15 September 1995.
  19. J. L. Cruz-Rivera, W. S. Lacy, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Performance modeling of optical interconnection technologies for massively parallel processing systems,” in Proceedings of the Third International Workshop on Massively Parallel Processing Using Optical Interconnections, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos Calif., 1996), pp. 264–275. [CrossRef]
  20. J. L. Cruz-Rivera, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Modeling the technology impact on the design of a two-level multicomputer interconnection network,” in Proceedings of the 1996 International Conference on Computer Design (IEEE Computer Society, Los Alamitos Calif., 1996), pp. 165–169.
  21. K. H. Calhoun, C. B. Camperi-Ginestet, N. M. Jokerst, “Vertical optical communication through stacked silicon wafers using hybrid monolithic thin film ingaasp emitters and detectors,” IEEE Photon. Technol. Lett. 5, 254–257 (1993). [CrossRef]
  22. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI (Addison-Wesley, Reading, Mass., 1990).
  23. J. W. Goodman, Introduction to Fourier Optics (McGraw-Hill, San Francisco, 1968).
  24. D. Zaleta, J. Fan, B. C. Kress, S. H. Lee, C. K. Cheng, “Optimum placement for optoelectronic multichip modules and the synthesis of diffractive optics for multichip module interconnects,” Appl. Opt. 33, 1444–1456 (1994). [CrossRef] [PubMed]
  25. D. S. Wills, H. H. Cat, J. L. Cruz-Rivera, W. S. Lacy, J. M. Baker, J. Eble, A. López-Lagunas, M. Hopper, “High throughput, low memory applications on the pica architecture,” IEEE Trans. Parallel Distrib. Syst. 8, 1055–1067 (1997). [CrossRef]
  26. J. L. Cruz-Rivera, E. V. R. Di Bella, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Parallelized formulation of the maximum likelihood-expectation maximization algorithm for fine-grain message-passing architectures,” IEEE Trans. Med. Imag. 14, 758–762 (1995). [CrossRef]
  27. G. A. Sai-Halsz, “Performance trends in high-end processors,” Proc. IEEE 83, 20–36 (1995). [CrossRef]
  28. V. J. Sferrino, “Multichip module study,” Tech. Rep. TR9545 (MIT Lincoln Laboratory, Lexington, Mass. 1992).
  29. K. Aoyama, A. A. Chien, “The cost of adaptivity and virtual lanes in a wormhole router,” VLSI Design 2(4), 315–333 (1995). [CrossRef]
  30. D. C. Edelstein, G. A. Sai-Halsz, Y.-J. Mii, “VLSI on-chip interconnection performance simulations and measurements,” IBM J. Res. Develop. 39, 383–401 (1995). [CrossRef]
  31. W. J. Dally, “Express (c)ubes: improving the performance of k-ary n-cube interconnection networks,” IEEE Trans. Comput. 40, 1016–1023 (1991). [CrossRef]
  32. R. T. Chen, H. Lu, D. Robinson, M. Wang, G. Savant, T. Jannson, “Guided-wave planar optical interconnects using highly multiplexed polymer waveguide holograms,” J. Lightwave Technol. 10, 888–897 (1992). [CrossRef]
  33. R. A. Soref, F. Namavar, E. Cortesi, L. Friedman, R. Lareau, “Vertical 3-d integration of silicon waveguides in Si–SiO2–Si–SiO2–Si structure,” in Microelectronic Interconnects and Packages: Optical and Electrical Technologies, G. Arjavalingam, J. Pazaris, eds., Proc. SPIE1389, 408–421 (1990). [CrossRef]
  34. F. Sauer, “Fabrication of diffractive–reflective optical interconnects for infrared operation based on total internal reflection,” Appl. Opt. 28, 386–388 (1989). [CrossRef] [PubMed]
  35. R. K. Kostuk, M. Kato, Y.-T. Huang, “Polarization properties of substrate mode holographic interconnects,” Appl. Opt. 29, 3848–3854 (1990). [CrossRef] [PubMed]
  36. W. S. Lacy, J. L. Cruz-Rivera, D. S. Wills, “The offset cube: a three-dimensional multicomputer network topology using through-wafer optics,” IEEE Trans. Parallel Distribut. Syst. (to be published).

Cited By

Alert me when this paper is cited

OSA is able to provide readers links to articles that cite this paper by participating in CrossRef's Cited-By Linking service. CrossRef includes content from more than 3000 publishers and societies. In addition to listing OSA journal articles that cite this paper, citing articles from other participating publishers will also be listed.

« Previous Article  |  Next Article »

OSA is a member of CrossRef.

CrossCheck Deposited