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Applied Optics

Applied Optics


  • Vol. 35, Iss. 8 — Mar. 10, 1996
  • pp: 1317–1327

Tolerancing of board-level-free-space optical interconnects

David Zaleta, Susant Patra, Volkan Ozguz, Jian Ma, and Sing H. Lee  »View Author Affiliations

Applied Optics, Vol. 35, Issue 8, pp. 1317-1327 (1996)

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For optical interconnects to become a mature technology they must be amenable to electronic packaging technology. Two main obstacles to including free-space optical interconnects are alignment and heat-dissipation issues. Here we study the issues of alignment tolerancing that are due to assembly and manufacturing variations (passive-element tolerancing) over long board-level distances (>10 cm) for free-space optical interconnects. We also combine these variations with active optoelectronic device variations (active-element tolerancing). We demonstrate a computer-aided analysis procedure that permits one to determine both active- and passive-element tolerances needed to achieve some system-level specification, such as yield or cost. The procedure that we employ relies on developing a detailed design of the system to be studied in a standard optical design program, such as CODE V. Using information from this model, we can determine the integrated power falling on the detector, which we term optical throughput, by performing Gaussian propagation or general Fresnel propagation (if significant vignetting occurs). This optical throughput can be used to determine system-level performance criteria, such as bit-error rate. With this computer-aided analysis technique, a sensitivity analysis of all the variations under study is made on a system with realistic board-level interconnect distances to find each perturbation's relative effects (with other perturbations set to 0) on the power falling on the detector. This information is used to set initial tolerances for subsequent tolerancing analysis and design runs. A tolerancing analysis by Monte Carlo techniques is applied to determine if the yield or cost (yield is defined as the percentage of systems that have acceptable system performance) is acceptable. With a technique called parametric sampling, a subsequent tolerancing design run can be applied to optimize this yield or cost with little increase in computation. We study a design example and show that most of the tolerances can be achieved with current technology.

© 1996 Optical Society of America

Original Manuscript: June 16, 1995
Revised Manuscript: September 25, 1995
Published: March 10, 1996

David Zaleta, Susant Patra, Volkan Ozguz, Jian Ma, and Sing H. Lee, "Tolerancing of board-level-free-space optical interconnects," Appl. Opt. 35, 1317-1327 (1996)

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