Advances in VLSI and optoelectronic multichip module technologiesare enabling the construction of ultracompact massively parallelprocessing systems. The technological parameters that define thewirability and delay characteristics of these technologies have asignificant impact on the system architecture. An analytical modelis presented that allows the design space exploration of theinterconnection networks associated with multinode chips packaged on asingle multichip module substrate. Possible system designs areevaluated for a two-level interconnect with separate k-aryn-cube networks for interchip and intrachipcommunication. The impact of several architectural andtechnological parameters on the optimal network implementation (based on average no-load latency) is analyzed.

© 1998 Optical Society of America

[Optical Society of America ]

You do not have subscription access to this journal. Citation lists with outbound citation links are available to subscribers only. You may subscribe either as an OSA member, or as an authorized user of your institution.

Contact your librarian or system administrator
or
Log in to access OSA Member Subscription

You do not have subscription access to this journal. Cited by links are available to subscribers only. You may subscribe either as an OSA member, or as an authorized user of your institution.

Contact your librarian or system administrator
or
Log in to access OSA Member Subscription

You do not have subscription access to this journal. Article level metrics are available to subscribers only. You may subscribe either as an OSA member, or as an authorized user of your institution.

Contact your librarian or system administrator
or
Log in to access OSA Member Subscription

Related Journal Articles

• Signal window minimum average error algorithm for computer-generated holograms (JOSAA)
• Space-Variant Interconnections Based on Diffractive Optical Elements for Neural Networks: Architectures and Cross-Talk Reduction (AO)
• Extensible, Low-Chromatic-Sensitivity, All-diffractive-Optics Relay for Interconnecting Optoelectronic Device Arrays (AO)
• Optoelectronic Neural-Network Scheduler for Packet Switches (AO)
• Design and Operation of an In Situ Microchannel Alignment-Detection System (AO)

Related Conference Papers

• Laser Writing of Tapers in Polymer
• Scaling VCSEL Reliability Up to 250Terabits/s of System Bandwidth
• Optical Interconnect Demonstrator with Embedded Waveguides and Butt-Coupled Optoelectronic Modules
• PAM-4 Signaling over VCSELs Using 0.13μm CMOS
• Laser Writing of Tapers in Polymer