Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.
© 2003 Optical Society of America
(050.1970) Diffraction and gratings : Diffractive optics
(200.2610) Optics in computing : Free-space digital optics
(200.4650) Optics in computing : Optical interconnects
(200.4880) Optics in computing : Optomechanics
Andrew G. Kirk, David V. Plant, Ted H. Szymanski, Zvonko G. Vranesic, Frank A. P. Tooley, David R. Rolston, Michael H. Ayliffe, Frederic K. Lacroix, Brian Robertson, Eric Bernier, and Daniel F.-Brosseau, "Design and Implementation of a Modulator-Based Free-Space Optical Backplane for Multiprocessor Applications," Appl. Opt. 42, 2465-2481 (2003)