OSA's Digital Library

Applied Optics

Applied Optics

APPLICATIONS-CENTERED RESEARCH IN OPTICS

  • Editor: Joseph N. Mait
  • Vol. 49, Iss. 36 — Dec. 20, 2010
  • pp: 6986–6994

Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capability

Daisaku Seto, Mao Nakajima, and Minoru Watanabe  »View Author Affiliations


Applied Optics, Vol. 49, Issue 36, pp. 6986-6994 (2010)
http://dx.doi.org/10.1364/AO.49.006986


View Full Text Article

Enhanced HTML    Acrobat PDF (1907 KB) Open Access





Browse Journals / Lookup Meetings

Browse by Journal and Year


   


Lookup Conference Papers

Close Browse Journals / Lookup Meetings

Article Tools

Share
Citations

Abstract

We present a proposal of a partial reconfiguration architecture for optically reconfigurable gate arrays and present an 11,424 gate dynamic optically reconfigurable gate array VLSI chip that was fabricated on a 96.04 mm 2 chip using an 0.35 μm three-metal complementary metal oxide semiconductor process technology. The fabricated VLSI chip achieved a 2.21 μs partial reconfiguration.

© 2010 Optical Society of America

OCIS Codes
(200.4660) Optics in computing : Optical logic
(230.2090) Optical devices : Electro-optical devices

ToC Category:
Optics in Computing

History
Original Manuscript: March 30, 2010
Revised Manuscript: September 15, 2010
Manuscript Accepted: September 23, 2010
Published: December 15, 2010

Citation
Daisaku Seto, Mao Nakajima, and Minoru Watanabe, "Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capability," Appl. Opt. 49, 6986-6994 (2010)
http://www.opticsinfobase.org/ao/abstract.cfm?URI=ao-49-36-6986


Sort:  Author  |  Year  |  Journal  |  Reset  

References

  1. Y. Pizhou and L. Chaodong, “A RISC CPU IP core,” in International Conference on Anti-Counterfeiting, Security and Identification (IEEE, 2008), pp. 356–359. [CrossRef]
  2. J. Goodacre and A. N. Sloss, “Parallelism and the ARM instruction set architecture,” Computer 38, 42–50 (2005). [CrossRef]
  3. T. Jamil, “RISC versus CISC,” IEEE Potentials 14, 13–16(1995). [CrossRef]
  4. D. B. Tolley, “Analysis of CISC versus RISC microprocessors for FDDI network interfaces,” in Conference on Local Computer Networks (IEEE, 1991), pp. 485–493.
  5. Altera Corporation, “Altera devices,” http://www.altera.com.
  6. Xilinx Inc., “Xilinx product data sheets,” http://www.xilinx.com.
  7. Lattice Semiconductor Corporation, “Lattice ECP and EC family data sheet” (2005), http://www.latticesemi.co.jp/products.
  8. P. Mal, P. D. Patel, and F. R. Beyette, “Design and demonstration of a fully integrated multi-technology FPGA: a reconfigurable architecture for photonic and other multi-technology applications,” IEEE Trans. Circuits Syst. I 56, 1182–1191(2009). [CrossRef]
  9. J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000). [CrossRef]
  10. J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24(1999). [CrossRef]
  11. J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” in 1999 Euro-American Workshop on Optoelectronic Information Processing, Critical Review Vol.  74 (SPIE, 1999), 265–288.
  12. M. Nakajima and M. Watanabe, “A four-context optically differential reconfigurable gate array,” J. Lightwave Technol. 27, 4460–4470 (2009). [CrossRef]
  13. M. Nakajima and M. Watanabe, “A 100-context optically reconfigurable gate array,” in IEEE International Symposium on Circuits and Systems (IEEE, 2010), pp. 2884–2887.
  14. M. Nakajima and M. Watanabe, “36-context dynamic optically reconfigurable gate array,” in IEEE International Symposium on System Integration (IEEE, 2009), pp. 19–23. [CrossRef]
  15. M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510–3515(2006). [CrossRef]
  16. M. Miyano, M. Watanabe, and F. Kobayashi, “Optically differential reconfigurable gate array,” Electron. Comput. Jpn. Part II 90, 132–139 (2007). [CrossRef]
  17. M. Watanabe, T. Shiki, and F. Kobayashi, “Scaling prospect of optically differential reconfigurable gate array VLSIs,” Analog Integr. Circ. Sig. Process. 60, 137–143, (2009). [CrossRef]
  18. D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array—perfect emulation,” IEEE J. Quantum Electron. 44, 493–500 (2008). [CrossRef]
  19. M. Watanabe and F. Kobayashi, “A logic synthesis and place and route environment for ORGAs,” in International Conference on Engineering of Reconfigurable Systems and Algorithms (2006), pp. 237–238.

Cited By

Alert me when this paper is cited

OSA is able to provide readers links to articles that cite this paper by participating in CrossRef's Cited-By Linking service. CrossRef includes content from more than 3000 publishers and societies. In addition to listing OSA journal articles that cite this paper, citing articles from other participating publishers will also be listed.


« Previous Article  |  Next Article »

OSA is a member of CrossRef.

CrossCheck Deposited