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Applied Optics

Applied Optics


  • Editor: Joseph N. Mait
  • Vol. 49, Iss. 36 — Dec. 20, 2010
  • pp: 6986–6994

Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capability

Daisaku Seto, Mao Nakajima, and Minoru Watanabe  »View Author Affiliations

Applied Optics, Vol. 49, Issue 36, pp. 6986-6994 (2010)

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We present a proposal of a partial reconfiguration architecture for optically reconfigurable gate arrays and present an 11,424 gate dynamic optically reconfigurable gate array VLSI chip that was fabricated on a 96.04 mm 2 chip using an 0.35 μm three-metal complementary metal oxide semiconductor process technology. The fabricated VLSI chip achieved a 2.21 μs partial reconfiguration.

© 2010 Optical Society of America

OCIS Codes
(200.4660) Optics in computing : Optical logic
(230.2090) Optical devices : Electro-optical devices

ToC Category:
Optics in Computing

Original Manuscript: March 30, 2010
Revised Manuscript: September 15, 2010
Manuscript Accepted: September 23, 2010
Published: December 15, 2010

Daisaku Seto, Mao Nakajima, and Minoru Watanabe, "Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capability," Appl. Opt. 49, 6986-6994 (2010)

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