OSA's Digital Library

Applied Optics

Applied Optics


  • Editor: Joseph N. Mait
  • Vol. 52, Iss. 9 — Mar. 20, 2013
  • pp: 1939–1946

Optical configuration acceleration on a new optically reconfigurable gate array very large scale integration using a negative logic implementation

Retsu Moriwaki and Minoru Watanabe  »View Author Affiliations

Applied Optics, Vol. 52, Issue 9, pp. 1939-1946 (2013)

View Full Text Article

Enhanced HTML    Acrobat PDF (10644 KB) Open Access

Browse Journals / Lookup Meetings

Browse by Journal and Year


Lookup Conference Papers

Close Browse Journals / Lookup Meetings

Article Tools



This paper presents a proposal of an optical configuration acceleration method applied to optically reconfigurable gate arrays (ORGAs) using a negative logic implementation. The gate array of an ORGA is reconfigured using a holographic memory. The reading time of a holographic memory depends on the number of bright bits included in a configuration context. The proposed optical configuration acceleration method can decrease the number of bright bits. As a result, the proposed optical configuration acceleration method can increase the reconfiguration frequency. In this paper, a fabricated ORGA very large scale integration that can support the optical configuration acceleration method is estimated. Consequently, this paper shows that the reconfiguration frequency of the proposed method is 1.97 times higher than those of conventional ORGA architectures with no increase of laser power.

© 2013 Optical Society of America

OCIS Codes
(090.2890) Holography : Holographic optical elements
(130.0250) Integrated optics : Optoelectronics
(130.3120) Integrated optics : Integrated optics devices
(130.3750) Integrated optics : Optical logic devices
(250.3140) Optoelectronics : Integrated optoelectronic circuits

ToC Category:

Original Manuscript: December 17, 2012
Manuscript Accepted: January 29, 2013
Published: March 15, 2013

Retsu Moriwaki and Minoru Watanabe, "Optical configuration acceleration on a new optically reconfigurable gate array very large scale integration using a negative logic implementation," Appl. Opt. 52, 1939-1946 (2013)

Sort:  Author  |  Year  |  Journal  |  Reset  


  1. Altera Corporation, “Altera unveils 28 nm Stratix V FPGA family,” http://www.altera.com .
  2. X. Wu, P. Gopalan, and G. Lara, “Xilinx next generation 28 nm FPGA technology overview,” http://www.xilinx.com .
  3. Xilinx Inc., “Xilinx product data sheets,” http://www.xilinx.com .
  4. T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.
  5. V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.
  6. E. Culurciello and A. G. Andreou, “Capacitive coupling of data and power for 3D silicon-on-insulator VLSI,” in IEEE International Symposium on Circuits and Systems (IEEE, 2005), pp. 4142–4145.
  7. R. Hentschke, G. Flach, F. Pinto, and R. Reis, “3D-Vias aware quadratic placement for 3D VLSI circuits,” in IEEE Computer Society Annual Symposium on VLSI (IEEE, 2007), pp. 67–72.
  8. P. Mal, P. D. Patel, and F. R. Beyette, “Design and demonstration of a fully integrated multi-technology FPGA: a reconfigurable architecture for photonic and other multi-technology applications,” IEEE Trans. Circuit. Sys. 56, 1182–1191 (2009). [CrossRef]
  9. J. V. Campenhout, H. V. Marck, J. Depreitere, and J. Dambre, “Optoelectronic FPGA’s,” IEEE J. Sel. Top. Quantum Electron. 5, 306–315 (1999). [CrossRef]
  10. F. Breyer, S. C. J. Lee, D. Cardenas, S. Randel, and N. Hanik, “Real-time gigabit ethernet transmission over up to 25 m Step-Index Polymer Optical Fibre using LEDs and FPGA based signal processing, ” presented at European Conference on Optical Communication, Vienna, Austria, 20–24 September 2009.
  11. H. Morita and M. Watanabe, “Microelectromechanical configuration of an optically reconfigurable gate array,” IEEE J. Quantum Electron. 46, 1288–1294 (2010). [CrossRef]
  12. M. Nakajima and M. Watanabe, “A four-context optically differential reconfigurable gate array,” IEEE/OSA J. Lightw. Technol. 27, 4460–4470 (2009). [CrossRef]
  13. D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array—perfect emulation,” IEEE J. Quantum Electron. 44, 493–500 (2008). [CrossRef]
  14. M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510–3515(2006). [CrossRef]

Cited By

Alert me when this paper is cited

OSA is able to provide readers links to articles that cite this paper by participating in CrossRef's Cited-By Linking service. CrossRef includes content from more than 3000 publishers and societies. In addition to listing OSA journal articles that cite this paper, citing articles from other participating publishers will also be listed.

« Previous Article  |  Next Article »

OSA is a member of CrossRef.

CrossCheck Deposited