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Journal of Display Technology

Journal of Display Technology

| A JOINT IEEE/OSA PUBLICATION

  • Vol. 8, Iss. 1 — Jan. 1, 2012
  • pp: 12–17

Oxide Thinning and Structure Scaling Down Effect of Low-Temperature Poly-Si Thin-Film Transistors

William Cheng-Yu Ma, Tsung-Yu Chiang, Je-Wei Lin, and Tien-Sheng Chao

Journal of Display Technology, Vol. 8, Issue 1, pp. 12-17 (2012)


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Abstract

In this paper, the gate oxide thickness, and the channel length and width of low-temperature poly-Si thin-film transistors (LTPS-TFTs) have been comprehensively studied. The scaling down of gate oxide thickness from 50 to 20 nm significantly improves the subthreshold swing (S.S.) of LTPS-TFTs from 1.797 V/decade to 0.780 V/decade and the threshold voltage VTH from 10.87 V to 5.00 V. Moreover, the threshold voltage VTH roll-off is also improved with the scaling down of gate oxide thickness due to gate capacitance density enhancement. The channel length scaling down also shows significant subthreshold swing S.S. improvement due to a decreasing of the channel grain boundary trap density Nt. However, the scaling down of channel length also increases the series resistance effect, resulting in the degradation of the field-effect mobility μFE. Therefore, the channel length dependence of field-effect mobility μFE is slightly different with different channel width due to the competition of channel grain boundary trap density effect and series resistance effect.

© 2011 IEEE

Citation
William Cheng-Yu Ma, Tsung-Yu Chiang, Je-Wei Lin, and Tien-Sheng Chao, "Oxide Thinning and Structure Scaling Down Effect of Low-Temperature Poly-Si Thin-Film Transistors," J. Display Technol. 8, 12-17 (2012)
http://www.opticsinfobase.org/jdt/abstract.cfm?URI=jdt-8-1-12

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