Abstract
Electrical characteristics of fully self-aligned gate overlapped lightly doped
drain (FSA-GOLDD) polysilicon thin-film transistors (TFTs), fabricated with a spacer
technology and providing submicron (0.35 μm) LDD regions, have been
analyzed. Device characteristics show negligible series resistance of the LDD region
while effective drain field relief has been demonstrated by a reduced kink effect and
off-current, if compared to conventional self-aligned (SA) devices. Short channel
effects are also mitigated by the LDD region, while substantial reduction in the
hot-carrier induced instability is found, when compared with conventional SA devices.
Optimum doping dose of the LDD region has been identified to be
9 × 10<sup>12</sup> cm<sup>2</sup>.
© 2011 IEEE
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