This paper reports a photolithographic process for fabricating organic field-effect transistors which provides two layers of metal with arbitrary via placement, and optionally allows for subtractive lithographic patterning of the transistor active layer. The demonstrated pentacene transistors have a field-effect mobility of 0.1 ± 0.05 cm2/(V·s). Parylene-C is used both as the gate dielectric and an encapsulation layer which allows for subtractive lithographic patterning. Also demonstrated is a PMOS inverter without level shifting circuitry and level-restoring VHigh and VLow. This work demonstrates a high definition, multilayer, integrated photolithographic process which creates organic field effect transistors suitable for use in integrated circuit applications such as a display backplanes.
© 2005 IEEE
Ioannis Kymissis, Akintunde Ibitayo Akinwande, and Vladimir Bulovic, "A Lithographic Process for Integrated Organic Field-Effect Transistors," J. Display Technol. 1, 289- (2005)