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Journal of Display Technology

Journal of Display Technology


  • Vol. 8, Iss. 1 — Jan. 1, 2012
  • pp: 23–26

Mechanisms of Threshold Voltage Shift in Polymorphous and Microcrystalline Silicon Bottom Gate Thin-Film Transistors

Maher Oudwan, Alexei Abramov, Dmitri Daineka, and Pere Roca i Cabarrocas

Journal of Display Technology, Vol. 8, Issue 1, pp. 23-26 (2012)

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In this paper, we have studied the stability of polymorphous silicon (pm-Si:H) and μc-Si:F:H bottom gate thin-film transistors (TFTs) by combining degradation and relaxation experiments under various stress conditions. We report on polymorphous silicon (pm-Si:H) TFTs with ΔVTH=1 V after 10 h of stress and μc-Si:F:H TFTs with superior stability, which show a ΔVTH of only 0.05 V under stress conditions similar to those encountered in active-matrix operation regime (VG=12 V and VD=10 V). Relaxation studies show that the quality of the interface between silicon nitride and pm-Si:H (or μc-Si:F:H) controls the stability at short stress times. Interestingly, the deposition conditions of the semiconductor layer seem to modify the quality of the a-SiN:H and thus the stability of the interface.

© 2011 IEEE

Maher Oudwan, Alexei Abramov, Dmitri Daineka, and Pere Roca i Cabarrocas, "Mechanisms of Threshold Voltage Shift in Polymorphous and Microcrystalline Silicon Bottom Gate Thin-Film Transistors," J. Display Technol. 8, 23-26 (2012)

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