This paper describes an analysis of bit error rate (BER) degradation due to a dip in the frequency response of an equalizing amplifier. An equivalent circuit simulation clarifies the BER degradation factors: 1) the output amplitude decrease of a specific binary sequence that has a repetition frequency equal to the dip frequency and 2) the oscillation in output voltage after rise and fall of signal level. A simple model shows that the center frequency and bandwidth of the dip as well as the depth of the dip strongly affect BER. A circuit simulation and experiment show that a dip at around one tenth the data rate causes the worst BER. The dip tolerance of a dc-suppressed transmission code is also discussed.
Mikio Yoneyama and Yukio Akazawa, "Bit Error Rate Degradation Due to a Dip in the Frequency Response of an Equalizing Amplifier," J. Lightwave Technol. 17, 1766- (1999)