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Journal of Lightwave Technology

Journal of Lightwave Technology


  • Vol. 22, Iss. 9 — Sep. 1, 2004
  • pp: 2021–

Power Comparison Between High-Speed Electrical and Optical Interconnects for Interchip Communication

Hoyeol Cho, Pawan Kapur, and Krishna C. Saraswat

Journal of Lightwave Technology, Vol. 22, Issue 9, pp. 2021- (2004)

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An I/O bandwidth commensurate with a dramatically increasing on-chip computational capability is highly desirable. Achieving this goal using board-level copper interconnects in the future will become increasingly challenging owing to severe increase in high-frequency,skin-effect and dielectric loss, noise due to crosstalk, impedance mismatch,and package reflections. The solutions designed to overcome these deleterious effects require complex signal processing at the interconnect endpoints, which results in a larger power and area requirement. Optical interconnects offer a powerful alternative, potentially at a lower power. Prior work in comparing the two technologies has entailed overly simplified assumptions pertaining to either the optical or the electrical system. In this paper, we draw a more realistic power comparison with respect to the relevant parameters such as bandwidth, interconnect length and bit error rate (BER) by capturing the essential complexity in both types of interconnect systems. At the same time, we preserve the simplicity by using mostly analytical models, verified by SPICE simulations where possible. We also identify critical device and system parameters, which have a large effect on power dissipation in each type of interconnect, while quantifying the severity of their impact. For optical interconnect, these parameters are detector and modulator capacitance, responsivity, coupling efficiency and modulator type; whereas, in the case of electrical system,the critical parameters include receiver sensitivity/offset and impedance mismatch. Toward this end, we first present an optimization scheme to minimize optical interconnect power and quantify its performance as a function of future technology nodes. Next, on the electrical interconnect side, we examine the power dissipation of a state-of-the-art electrical interconnect, which uses simultaneous bidirectional signaling with transmitter equalization and on-chip noise cancellation. Finally, we draw extensive comparisons between optical and electrical interconnects. As an example, for bandwidth of 6 Gb/s at 100 nm technology node, lengths greater than the critical length of about 43 cm yields lower power in optical interconnects. This length becomes lower (making optics more favorable) with higher data rates and lower bit error rate requirement.

© 2004 IEEE

Hoyeol Cho, Pawan Kapur, and Krishna C. Saraswat, "Power Comparison Between High-Speed Electrical and Optical Interconnects for Interchip Communication," J. Lightwave Technol. 22, 2021- (2004)

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  1. Y. Li, E. Towe and M. W. Haney, "Special issue on optical interconnections for digital systems", Proc. IEEE , vol. 88, pp. 723-727, June 2000.
  2. P. Kapur and K. C. Saraswat, "Comparisons between electrical and optical interconnects for on-chip signaling", in Int. Interconnect Technology Conf., 2002, pp. 89-91.
  3. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Reading, MA: Addison-Wesley, 1990.
  4. R. Ho, K. Mai and M. Horowitz, "Efficient on-chip global interconnects", in Symp. VLSI Circuits , 2003, pp. 271-274.
  5. K. Mai, T. Paaske, N. Jayasena, R. Ho, W. J. Dally and M. Horowitz, "Smart memories: A modular reconfigurable architecture", in Proc. 27th Int. Symp. Computer Architecture, 2000, pp. 161- 171.
  6. D. Hwang, T. Sze, A. Landin, R. Lytel and H. L. Davidson, "Optical interconnects: Out of the box forever?", J. Select. Topics Quantum Electron., vol. 9, no. 2, pp. 614 -623, Mar. 2003.
  7. R. Mooney, "Scaling methods for electrical interconnects to meet the performance requirements of microprocessor platforms", in 14th Annual Workshop on Interconnects Within High Speed Digital Syst., 2003.
  8. R. T. Chen, L. Lin, C. Choi, Y. J. Liu, B. Bihari, L. Wu, S. Tang, R. Wickman, B. Picor, M. K. Hibbs-brenner, J. Bristow and Y. S. Liu, "Fully embedded board-level guided-wave optoelectronic interconnects", Proc. IEEE, vol. 88, pp. 780-793, June 2000.
  9. Y. Li, J. Ai and J. Popelek, "Board-level 2-D data-capable optical interconnect circuits using polymer fiber-image guides", Proc. IEEE, vol. 88, pp. 794-805, 2000.
  10. T. May, A. G. Kirk, D. V. Plant, J. F. Ahadian, C. G. Fonstad, K. L. Lear, K. Tatah, M. S. Robinson and J. A. Trezza, "Interconnection of a two-dimensional array of vertical-cavity surface-emitting lasers to a receiver array by means of a fiber image guide", Appl. Opt., vol. 39, no. 5, pp. 683-689, Feb. 2000.
  11. K. P. Jackson, "High-density, array, optical interconnects for multi-chip modules", in Multi-Chip Module Conf., Mar. 1992, pp. 142-145.
  12. G. A. Keeler, B. E. Nelson, D. Agarwal and D. A. B. Miller, "Optical interconnects using short optical pulses", in Lasers and Electro-Opt. Soc. 12th Ann. Meet., 1999.
  13. Y. Liu, E. M. Strzelecka, J. Nohava, M. K. Hibbs-brenner and E. Towe, "Smart-pixel array technology for free-space optical interconnects", Proc. IEEE, vol. 88, pp. 764-768, 2000.
  14. D. V. Plant and A. G. Kirk, "Optical interconnects at the chip and board level: Challenges and solutions", Proc. IEEE, vol. 88, pp. 806-818, 2000.
  15. S. C. Esener, "Implementation and prospects for chip-to-chip free-space optical interconnects", in Int. Electron Devices Meet., 2001.
  16. A. V. Mule, A. Naeemi, E. N. Glytsis, T. K. Gaylord and J. D. Meindl, "Toward a comparison between chip-level optical interconnection and board-level exterconnection", in Interconnect Technol. Conf., June 2002, pp. 92-94.
  17. A. Naeemi, A. V. Mule and J. D. Meindl, "Partition length between board-level electrical and optical interconnects", in Interconnect Technol. Conf., June 2003, pp. 230-232.
  18. D. A. B. Miller, "Rationale and challenges for optical interconnects to electronic chips", Proc. IEEE, vol. 88, pp. 728-749, 2000.
  19. M. R. Feldman, S. C. Esener, C. C. Guest and S. H. Lee, "Comparison between optical and electrical interconnects based on power and speed considerations", Appl. Opt., vol. 27, no. 9, pp. 1742-1751, May 1988.
  20. M. Yoneyama, K. Takahata, T. Otsuji and Y. Akazawa, "Analysis and application of a novel model for estimating power dissipation of optical interconnections as a function of transmission bit error rate", J. Lightwave Technol., vol. 14, pp. 13-22, 1996.
  21. O. Kibar, D. A. A. Blerkon, C. Fan and S. C. Esener, "Power minimization and technology comparison for digital free-space optoelectronic interconnects", J. Lightwave Technol., vol. 17, pp. 546-555, Apr. 1999 .
  22. P. Kapur and K. C. Saraswat, "Minimizing power dissipation in chip to chip optical interconnects using optimal modulators and laser power", in Interconnect Technol. Conf., June 2003, pp. 224-226.
  23. P. K. Tien, "Light waves in thin films and integrated optics", Appl. optics, vol. 10, no. 11, pp. 2395-2413, 1971.
  24. A. V. Krishnamoorthy and D. A. B. Miller, "Scaling optoelectronic-VLSI circuits into the 21st century: A technology roadmap", IEEE J. Select. Topics Quantum Electron., vol. 2, pp. 55-76, Apr. 1996.
  25. P. Kapur and K. C. Saraswat, "Power dissipation in optical clock distribution network for high performance ICs", in Int. Interconnect Technol. Conf., 2002, pp. 151-153.
  26. International Technology Roadmap for Semiconductor , 1999 ed. San Jose, CA: Semiconductor Industry Assoc.,
  27. W. J. Dally and J. H. Poulton, Digital Systems Engineering, Cambridge, MA: Cambridge Univ. Press, 1998.
  28. W. J. Dally and J. Poulton, "Transmitter equalization for 4 Gbps Signaling", IEEE Micro, pp. 48-56, 1997.
  29. K. Y. K. Chang, J. Wei, C. Huang, S. Li, K. Donnelly, M. Horowitz, Y. Li and S. Sidiropoulos, "A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs", J. Solid-State Circuits, vol. 38, no. 5, pp. 747-754, May 2003.
  30. G. Ahn, D. K. Jeong and G. Kim, "A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminator for high-speed NRZ data transmission", IEEE J. Solid State Circuits, vol. 35, pp. 915-918, June 2000.
  31. B. K. Casper, H. Haycock and R. Mooney, "An accurate and efficient method for multi-Gb/s chip-to-chip signaling schemes", in Symp. VLSI Circuits, 2002, pp. 54-57.
  32. M. J. E. Lee, W. Dally and P. Chiang, "A 90 mW 4 Gb/s equalized I/O circuits with input offset cancellation", in Int. Solid-State Circuits Conf., 2000, pp. 252-253.
  33. C. Svensson and G. D. Dermer, "Time domain modeling of lossy interconnects", Trans. Adv. Packag. , vol. 23, no. 2, pp. 191-196, May 2001.
  34. D. A. B. Miller and H. M. Ozaktas, "Limit to the bit-rate capacity of electrical interconnect from the aspect ratio of the system architecture", J. Parallel Distrib. Comput., vol. 41, 1997.

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