There is a strong need for a methodology that minimizes total power, which inherently includes device design, for short-distance optical link applications (chip-to-chip or board-to-board communications). We present such a power optimization methodology for a modulator-based optical link, where we do a full 3-D modulator parameter optimization, keeping the power of the entire link in mind. We find for low bit rates (10 Gb/s) that the optimum operational voltage for the modulator was within the supply voltage at the 65-nm technology node. At higher bit rates, the optimum voltage is found to increase and go beyond the stipulated supply voltage. In such a case, a suboptimum operation at the supply voltage incurs a 46% power penalty at 25 Gb/s. Having obtained the optimum modulator design and operation parameters and the corresponding total link power dissipation, we examine the impact of device and system parameters on the optimization. We find that a smaller device capacitance is an efficient solution to push the optimum swing voltage to be within the supply voltage. This is feasible using monolithically integrated Ge-based complementary-metal–oxide–semiconductor-compatible modulator and metal–semiconductor–metal photodetectors.
© 2007 IEEE
Hoyeol Cho, Pawan Kapur, and Krishna C. Saraswat, "A Modulator Design Methodology Minimizing Power Dissipation in a Quantum Well Modulator-Based Optical Interconnect," J. Lightwave Technol. 25, 1621-1628 (2007)