OSA's Digital Library

Journal of Lightwave Technology

Journal of Lightwave Technology


  • Vol. 25, Iss. 6 — Jun. 1, 2007
  • pp: 1621–1628

A Modulator Design Methodology Minimizing Power Dissipation in a Quantum Well Modulator-Based Optical Interconnect

Hoyeol Cho, Pawan Kapur, and Krishna C. Saraswat

Journal of Lightwave Technology, Vol. 25, Issue 6, pp. 1621-1628 (2007)

View Full Text Article

Acrobat PDF (455 KB)

Browse Journals / Lookup Meetings

Browse by Journal and Year


Lookup Conference Papers

Close Browse Journals / Lookup Meetings

Article Tools

  • Export Citation/Save Click for help


There is a strong need for a methodology that minimizes total power, which inherently includes device design, for short-distance optical link applications (chip-to-chip or board-to-board communications). We present such a power optimization methodology for a modulator-based optical link, where we do a full 3-D modulator parameter optimization, keeping the power of the entire link in mind. We find for low bit rates (10 Gb/s) that the optimum operational voltage for the modulator was within the supply voltage at the 65-nm technology node. At higher bit rates, the optimum voltage is found to increase and go beyond the stipulated supply voltage. In such a case, a suboptimum operation at the supply voltage incurs a 46% power penalty at 25 Gb/s. Having obtained the optimum modulator design and operation parameters and the corresponding total link power dissipation, we examine the impact of device and system parameters on the optimization. We find that a smaller device capacitance is an efficient solution to push the optimum swing voltage to be within the supply voltage. This is feasible using monolithically integrated Ge-based complementary-metal–oxide–semiconductor-compatible modulator and metal–semiconductor–metal photodetectors.

© 2007 IEEE

Hoyeol Cho, Pawan Kapur, and Krishna C. Saraswat, "A Modulator Design Methodology Minimizing Power Dissipation in a Quantum Well Modulator-Based Optical Interconnect," J. Lightwave Technol. 25, 1621-1628 (2007)

Sort:  Year  |  Journal  |  Reset


  1. International Technology Roadmap for Semiconductors (2003) http://public.itrs.net.
  2. D. A. B. Miller, "Rationale and challenges for optical interconnects to electronic chips," Proc. IEEE 88, 728-749 (2000).
  3. H. M. Ozaktas, D. A. B. Miller, "Limit to the bit-rate capacity of electrical interconnect form the aspect ratio of the system architecture," J. Parallel Distrib. Comput. 41, 42-52 (1997).
  4. C. Svensson, G. D. Dermer, "Time domain modeling of lossy interconnects," IEEE Trans. Adv. Packag. 23, 191-196 (2001).
  5. W. J. Dally, J. Poulton, "Transmitter equalization for 4 Gbps signaling," IEEE Micro 17, 48-56 (1997).
  6. M. Haycock, R. Mooney, "3.2 GHz 6.4 Gb/s per wire signaling in a 0.18 μm CMOS ," Proc. Int. Solid-State Circuits Conf. (2001) pp. 62-63.
  7. R. Mooney, "Scaling methods for electrical interconnects to meet the performance requirements of microprocessor platforms," Proc. 14th Annu. Workshop Interconnects Within High Speed Digital Syst. (2003).
  8. H. Y. Cho, P. Kapur, K. C. Saraswat, "Power comparison between high-speed electrical and optical interconnects for inter-chip communication," J. Lightw. Technol. 22, 2021-2033 (2004).
  9. D. T. Neilson, "Optimization and tolerance analysis QCSE modulator and detectors," IEEE J. Quantum Electron. 33, 1094-1193 (1997).
  10. O. Kibar, D. A. A. Blerkon, C. Fan, S. C. Easner, "Power optimization and technology comparison for digital free-space optoelectronics interconnects ," J. Lightw. Technol. 17, 546-555 (1999).
  11. P. Kapur, R. D. Kekatpure, K. C. Saraswat, "Minimizing power dissipation in optical interconnects at low voltage using optimal modulator design," IEEE Trans. Electron Devices 52, 1713-1721 (2005).
  12. K. W. Goossen, J. E. Cunningham, W. Y. Jan, "Electroabsorption in ultranarrow-barrier GaAs/AlGaAs multiple quantum well modulators ," Appl. Phys. Lett. 64, 1071-1073 (1994).
  13. A. V. Krishnamoorthy, D. A. B. Miller, "Scaling optoelectronic VLSI circuits into the 21st century: A technology roadmap," IEEE J. Sel. Topics Quantum Electron. 2, 55-76 (1996).
  14. C. R. Pollock, Fundamentals of Optoelectronics (Irwin, 1995).
  15. J. J. Morikuni, A. Dharchoudhury, Y. Leblebici, S. M. Kang, "Improvements to the standard theory for photoreceiver noise," J. Lightw. Technol. 12, 1174-1184 (1994).
  16. G. F. Williams, Topics in Lightwave Transmission Systems (Academic, 1991).
  17. H. Y. Cho, P. Kapur, K. C. Saraswat, "Impact of technology node on power comparison for high-speed electrical and optical interconnects ," Proc. Int. Interconnect Tech. Conf. (2005) pp. 177-179.
  18. Y. H. Kuo, Y. K. Lee, Y. Ge, S. Ren, J. E. Roth, T. I. Kamins, D. A. B. Miller, J. S. Harris, "Strong quantum-confined Stark effect in germanium quantum-well structures on silicon ," Nature 437, 1334-1336 (2005).
  19. D. Buca, "Metal–germanium–metal ultrafast infrared detectors," J. Appl. Phys. 92, 7599-7605 (2002).
  20. C. O. Chui, A. K. Okyay, K. C. Saraswat, "Effective dark current suppression with asymmetric MSM photodetectors in Group IV semiconductors ," IEEE Photon. Technol. Lett. 15, 1585-1587 (2003).

Cited By

OSA is able to provide readers links to articles that cite this paper by participating in CrossRef's Cited-By Linking service. CrossRef includes content from more than 3000 publishers and societies. In addition to listing OSA journal articles that cite this paper, citing articles from other participating publishers will also be listed.

« Previous Article  |  Next Article »

OSA is a member of CrossRef.

CrossCheck Deposited