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Journal of Lightwave Technology

Journal of Lightwave Technology

| A JOINT IEEE/OSA PUBLICATION

  • Vol. 27, Iss. 21 — Nov. 1, 2009
  • pp: 4634–4641

Multidimensional and Reconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems

Avinash Karanth Kodi and Ahmed Louri

Journal of Lightwave Technology, Vol. 27, Issue 21, pp. 4634-4641 (2009)


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Abstract

The increasing demand for higher communication bandwidth, reduced power consumption, and increased reliability combined with fundamental electrical signalling limitations is leading the drive for optics as an interconnect technology of choice for high-performance computing (HPC) systems. However, failure in any optical link can completely disrupt communication by isolating processing nodes in HPC systems. Moreover, while static allocation of wavelengths (channels) provides every node with equal opportunity for communication, it can also lead to network congestion for nonuniform traffic patterns. In this paper, we propose a multidimensional optoelectronic architecture, called ${nD}$-reconfigurable, all-photonic interconnect for distributed and parallel systems (${n}$dimensional-RAPID) where ${n}$ can be 1, 2, or 3. ${nD}$-RAPID exploits optical architecture and technology design space that simultaneously tackles both fault-tolerance and dynamic bandwidth reallocation (DBR) of system architecture. Fault-tolerance in ${nD}$-RAPID is enabled through a multidimensional architecture. DBR is implemented by the row–column switching matrix using silicon-on-insulator (SOI)-based microring resonators that adapts to changes in communication patterns at runtime. Simulation results indicate that ${nD}$-RAPID outperformed other electrical networks for most traffic patterns. Results on DBR show that the proposed row–column switch organization significantly improves throughput and latency with a slight increase in electrical power consumption ($\sim$0.4% for the worst case traffic).

© 2009 IEEE

Citation
Avinash Karanth Kodi and Ahmed Louri, "Multidimensional and Reconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems," J. Lightwave Technol. 27, 4634-4641 (2009)
http://www.opticsinfobase.org/jlt/abstract.cfm?URI=jlt-27-21-4634


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References

  1. D. A. B. Miller, "Rationale and challenges for optical interconnects to electronic chips," Proc. IEEE 88, 728-749 (2000).
  2. R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, R. S. Williams, "Nanoelectronic and nanophotonic interconnect," Proc. IEEE 96, 230-247 (2008).
  3. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, K. Asanovic, "Building manycore processor-to-dram networks with monolithic silicon photonics," Proc. 16th Annu. Symp. High-Performance Interconnects (2008).
  4. N. Kirman, M. Kirman, R. K. Dokania, J. Martínez, A. B. Apsel, M. A. Watkins, D. H. Albonesi, "Leveraging optical technology in future bus-based chip multiprocessors," Proc. 39th Int. Symp. Microarchitecture (2006).
  5. A. Shacham, K. Bergman, L. P. Carloni, "On the design of a photonic network-on-chip," Proc. 1st Int. Symp. Network-on-Chip (2007) pp. 53-64.
  6. D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, J. H. Ahn, "Corona: System implications of emerging nanophotonic technology," Proc. 35th Int. Symp. Comput. Architecture (2008).
  7. A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kuchta, M. B. Ritter, "Exploitation of optical interconnects in future server architectures," IBM J. Res. Develop. 49, 755-775 (2005).
  8. S. Banerjee, D. Sarkar, "Hypercube connected rings: A scalable and fault-tolerant logical topology for optical networks," Comput. Commun. 24, 1060-1079 (2001).
  9. Y. Yang, J. Wang, "A fault-tolerant rearrangable permutation network," IEEE Trans. Comput. 53, 414-426 (2004).
  10. B. Helvik, R. Andreassen, "Fault tolerance in optical networks; a study of electronic in- and egress interconnections in torus topologies," Proc. 9th Conf. Opt. Network Design Model. (2005).
  11. A. K. Kodi, A. Louri, "Rapid: Reconfigurable and scalable all-photonic interconnect for distributed shared memory multiprocessors," J. Lightw. Technol. 22, 2101-2110 (2004).
  12. P. Dowd, J. Perreault, J. Chu, D. Crouse, D. Hoffmeister, R. Minnich, D. Burns, F. Hady, Y. J. Chen, M. Dagenais, D. Stone, "Lightning network and systems architecture," J. Lightw. Technol. 14, 1371-1387 (1996).
  13. C. M. Qiao, R. Melham, D. Chiarulli, S. Levitan, "Dynamic reconfiguration of optically interconnected networks with time-division multiplexing," J. Parallel Distrib. Comput. 22, 268-278 (1994).
  14. P. Krishnamurthy, R. Chamberlain, M. Franklin, "Dynamic reconfiguration of an optical interconnect," Proc. 36th Annu. Simul. Symp. (2003).
  15. A. K. Kodi, A. Louri, "Performance adaptive power-aware reconfigurable optical interconnects for high-performance computing (HPC) systems," Int. Conf. High-Performance Comput. Netw. Storage Anal. (2007).
  16. Q. Xu, B. Schmidt, S. Pradhan, M. Lipson, "Micrometre-scale silicon electro-optic modulator," Nature Lett. 435, 325-327 (2005).
  17. B. A. Small, B. G. Lee, K. Bergman, Q. Xu, M. Lipson, "Multiple-wavelength integrated photonic networks based on microring resonator devices," J. Opt. Netw. 6, 112-120 (2007).
  18. C. Berger, B. J. Offrein, M. Schmatz, "Challenges for the introduction of board-level optical interconnect technology into product development roadmaps," Proc. SPIE—Int. Soc. Opt. Eng. (2006) pp. 61240.J1-61240.J12.
  19. M. Haurylau, G. Chen, H. Chen, J. Zhang, N. A. Nelson, D. H. Albonesi, E. G. Friedman, P. M. Fauchet, "On-chip optical interconnect roadmap: Challenges and critical directions," IEEE J. Sel. Top. Quantum Electron. 12, 1699-1705 (2006).
  20. A. L. Glebov, M. G. Lee, K. Yokouchi, "Integration technologies for pluggable backplane optical interconnect systems," Opt. Eng. 64, (2007).
  21. C. Gunn, "CMOS photonics for high speed interconnects," IEEE Photon. Technol. Lett. 26, 58-66 (2006).
  22. P. Dumon, W. Bogaerts, D. Van Thourhout, D. Taillaert, R. Baets, "Compact wavelength router based on a silicon-on-insulator arrayed waveguide grating pigtalied to a fiber array," Opt. Express 14, 664-669 (2006).
  23. A. Huang, C. Gunn, G. Li, Y. Liang, S. Mirsaidi, A. Narasimha, T. Pinguet, "10 Gb/s photonic modulator and WDM mux/demux integrated with electronics in 0.13 $\mu {\hbox {m}}$ soi CMOS," Proc. IEEE Int. Solid-State Circuits Conf. (2006).
  24. H. J. J. Yeh, J. S. Smith, "Integration of Gaas vertical cavity surface emitting laser on Si by substrate removal," Appl. Phys. Lett. 64, 1466-1468 (1994).
  25. A. V. Krishnamoorthy, K. W. Goossen, L. M. F. Chirovsky, R. G. Rozier, P. Chandramani, S. P. Hui, J. Lopata, J. A. Walker, L. A. D'Asaro, "16$\,\times\,$16 VCSEL array flip-chip bonded to CMOS VLSI circuit," IEEE Photon. Technol. Lett. 12, 1073-1075 (2000).
  26. A. Kodi, A. Louri, "A system simulation methodology of optical interconnects for high-performance computing (HPC) systems," J. Opt. Netw. 6, 1282-1300 (2007).
  27. M. Galles, "Spider: A high-speed network interconnect," IEEE Micro 17, 34-39 (1997).

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