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Journal of Lightwave Technology

Journal of Lightwave Technology

| A JOINT IEEE/OSA PUBLICATION

  • Vol. 30, Iss. 19 — Oct. 1, 2012
  • pp: 3173–3181

FPGA-Based Label Processor for Low Latency and Large Port Count Optical Packet Switches

Nicola Calabretta

Journal of Lightwave Technology, Vol. 30, Issue 19, pp. 3173-3181 (2012)


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Abstract

We present a field-programmable gate array (FPGA)-based label processor for in-band optical labels with a processing time independent of the number of label bits. This allows for implementing an optical packet switching architecture that scales to a large port count without compromising the latency. As a proof of concept, we have employed an FPGA board with 100 MHz clock to validate the operation of the label processor in a 160 Gb/s optical packet switching system. Experimental results show successful three label bits processing and 160 Gb/s packets switching with 1 dB power penalty and 470 ns of latency. Projections on the label processor performance by using more powerful FPGAs indicate that 60 label bits (260 optical addresses) can be processed within 31 ns.

© 2012 IEEE

Citation
Nicola Calabretta, "FPGA-Based Label Processor for Low Latency and Large Port Count Optical Packet Switches," J. Lightwave Technol. 30, 3173-3181 (2012)
http://www.opticsinfobase.org/jlt/abstract.cfm?URI=jlt-30-19-3173

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