Silicon photonic interconnects offer a promising solution to meeting the ever growing demand for more efficient I/O bandwidth density. We report an ultralow power 80 Gb/s arrayed silicon photonic transceiver for dense, large bandwidth inter/intrachip interconnects. Low parasitic microsolder-based hybrid bonding enables close integration of silicon photonic array devices optimized on a 130 nm silicon-on-insulator CMOS platform with CMOS very large scale integration circuits optimized on a 40 nm silicon CMOS platform to achieve unprecedented energy efficiency. The hybrid CMOS transceiver consists of eight 10 Gb/s channels with a total consumed power below 6 mW/channel. The eight-channel wavelength division multiplexing transmitter array using cascaded tunable ring modulators demonstrated better than 100 fJ/bit energy efficiency for 10 Gb/s operation excluding the laser power and tuning power, while the eight-channel receiver array using broadband Ge p-i-n waveguide detectors show sensitivity of better than -15 dBm for a bit error rate of 10-12 at a data rate of 10 Gb/s with energy efficiency of better than 500fJ/bit.
© 2011 IEEE
Xuezhe Zheng, Frankie Y. Liu, Jon Lexau, Dinesh Patil, Guoliang Li, Ying Luo, Hiren D. Thacker, Ivan Shubin, Jin Yao, Kannan Raj, Ron Ho, John E. Cunningham, and Ashok V. Krishnamoorthy, "Ultralow Power 80 Gb/s Arrayed CMOS Silicon Photonic Transceivers for WDM Optical Links," J. Lightwave Technol. 30, 641-650 (2012)