Abstract
We demonstrate WDM-enabled all-passive optical row and column address selector (RAS/CAS) circuits for
use as optical static RAM (SRAM) bank peripherals in future optical cache memory implementations. We show that the
introduction of the wavelength dimension in both the memory address and data word fields can lead to RAS and CAS
architectures that rely exclusively on all-passive wavelength-selective configurations. An all-optical 2 × 4 RAS
comprising a wavelength-selective filtering matrix (λ-matrix) and a wavelength-based CAS unit formed by a
simple AWG element are demonstrated in proof-of-principle experiments at 10 Gb/s with error-free operation at 10
$^{-9}$
BER value using two different types of WDM SRAM row Access
Gate (AG): a cross-phase modulation SOA-MZI gate and a single SOA cross-gain modulation gate, with the first providing
the higher performance compared to SOA module and the second offering lower power requirements between the two WDM AG.
A chip-scale optical cache peripheral circuitry development path using Silicon-on-Insulator (SOI) ring resonators for
the λ-matrix implementation is also presented and the proposed architecture is evaluated via physical layer
simulations using SOAs as SRAM row AGs at 10 Gb/s for a 16×4 optical SRAM bank. Moreover, we discuss on
possible improvements towards reducing insertion losses of the RAS/CAS modules in order to allow for increased block
sizes. Finally, we provide a detailed analysis on the design and parameter specifications required for RAS and CAS
block size scaling towards supporting higher-capacity optical SRAM banks.
© 2013 IEEE
PDF Article
More Like This
Cited By
You do not have subscription access to this journal. Cited by links are available to subscribers only. You may subscribe either as an Optica member, or as an authorized user of your institution.
Contact your librarian or system administrator
or
Login to access Optica Member Subscription