Digital reconfigurable optical add–drop multiplexer systems are characterized by optical–electrical–optical (OEO) conversion of wavelength division multiplexing line wavelengths and by an electronic switching providing wavelength routing. The recent implementation of monolithically integrated large-scale photonic integrated circuits (PICs) in indium phosphide of terabit capacity cross-point switches and of high-capacity optical transport network (OTN) processor chips has allowed not only a considerable reduction in cost and power consumption of the OEO conversion stage but has also enabled the integration, in the same hardware, of OTN sub-wavelength switching and wavelength switching. To reduce the switching fabric complexity, we propose and investigate the structure of a scalable switch core composed of a space switching fabric routing only signals at a higher rate (high-order optical channel data unit (ODU)) and by OTN time–space switching fabrics switching both signals at a lower rate (low-order ODU) and a higher rate (high-order ODU). The lower hardware complexity of the proposed switching fabric is to be paid with a sub-flow blocking that we have investigated by introducing an analytical model validated by simulation. The blocking performance is evaluated as a function of the main switch and traffic parameters and under some traffic aggregation and routing policies. We show that in some traffic scenarios the blocking probability can reach a value of $10^{-8}$ if suitable resource management policies are adopted.