A novel 3D stacking method for Opto-electronic dies on CMOS ICs

doi:10.1364/OE.20.00B386

A novel 3D stacking method for Opto-electronic dies on CMOS ICs

Pinxiang Duan, Oded. Raz, Barry. E. Smalbrugge, Jeroen Duis, and Harm. J. S Dorren »View Author Affiliations

Optics Express, Vol. 20, Issue 26, pp. B386-B392 (2012)
http://dx.doi.org/10.1364/OE.20.00B386

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Abstract

A high speed, high density and potentially low cost solution for realizing a compact transceiver module is presented in this paper. It is based on directly bonding an Opto-electronic die on top of CMOS IC chip and creating a photoresist ramp to bridge the big step (around 220μm) from Opto-electronic pads to CMOS IC pads. The required electrical connection between them is realized lithographically with a process than can be scaled to full wafer production. A 12-channel transmitter based on the technique was fabricated and test shows good performance up to 12.5 Gb/s/ch.

OCIS Codes
(130.0250) Integrated optics : Optoelectronics
(130.3120) Integrated optics : Integrated optics devices
(200.0200) Optics in computing : Optics in computing
(200.4650) Optics in computing : Optical interconnects
(220.3740) Optical design and fabrication : Lithography
(140.7260) Lasers and laser optics : Vertical cavity surface emitting lasers

ToC Category:
Waveguide and Optoelectronic Devices

History
Original Manuscript: October 3, 2012
Revised Manuscript: November 11, 2012
Manuscript Accepted: November 11, 2012
Published: November 29, 2012

Virtual Issues
European Conference on Optical Communication 2012 (2012) Optics Express

Citation
Pinxiang Duan, Oded. Raz, Barry. E. Smalbrugge, Jeroen Duis, and Harm. J. S Dorren, "A novel 3D stacking method for Opto-electronic dies on CMOS ICs," Opt. Express 20, B386-B392 (2012)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-20-26-B386

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References

D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE88(6), 728–749 (2000). [CrossRef]
D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE97(7), 1166–1185 (2009). [CrossRef]
H. J. S. Dorren, P. Duan, O. Raz, and R. P. Luijten, “Fundamental bounds for photonic interconnects,” 13th International Conference on Transparent Optical Networks (ICTON, Stockholm, 2011), paper Mo.C1.1.
L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, and M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng.87(5-8), 1210–1212 (2010). [CrossRef]
C. L. Schow, F. E. Doany, A. V. Rylyakov, B. G. Lee, C. V. Jahnes, Y. H. Kwark, C. W. Baks, D. M. Kuchta, and J. A. Kash, “A 24-Channel, 300 Gb/s, 8.2 pJ/bit, full-duplex fiber-coupled optical transceiver module based on a single “Holey” CMOS IC,” J. Lightwave Technol.29(4), 542–553 (2011). [CrossRef]
F. E. Doany, B. G. Lee, A. V. Rylyakov, D. M. Kuchta, C. Baks, C. Jahnes, F. Libsch, and C. L. Schow, “Terabit/sec VCSEL-based parallel optical module based on Holey CMOS transceiver IC”. In Proceeding of the Optical Fiber communication conference (OFC/NFOEC, Los Angeles, 2012), PDP5D.9.
P. Duan, O. Raz, B. E. Smalbrugge, J. Duis, and H. J. S. Dorren, “Chip-to-chip interconnects based on 3D stacking of opto-electrical dies on Si, ” in the Proc. SPIE. 8267, Optoelectronic Interconnects XII, 82670U (San Francisco, 2012).

J. Lightwave Technol.

C. L. Schow, F. E. Doany, A. V. Rylyakov, B. G. Lee, C. V. Jahnes, Y. H. Kwark, C. W. Baks, D. M. Kuchta, and J. A. Kash, “A 24-Channel, 300 Gb/s, 8.2 pJ/bit, full-duplex fiber-coupled optical transceiver module based on a single “Holey” CMOS IC,” J. Lightwave Technol.29(4), 542–553 (2011). [CrossRef]

Microelectron. Eng.

L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, and M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng.87(5-8), 1210–1212 (2010). [CrossRef]

Proc. IEEE

D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE88(6), 728–749 (2000). [CrossRef]
D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE97(7), 1166–1185 (2009). [CrossRef]

Other

H. J. S. Dorren, P. Duan, O. Raz, and R. P. Luijten, “Fundamental bounds for photonic interconnects,” 13th International Conference on Transparent Optical Networks (ICTON, Stockholm, 2011), paper Mo.C1.1.
F. E. Doany, B. G. Lee, A. V. Rylyakov, D. M. Kuchta, C. Baks, C. Jahnes, F. Libsch, and C. L. Schow, “Terabit/sec VCSEL-based parallel optical module based on Holey CMOS transceiver IC”. In Proceeding of the Optical Fiber communication conference (OFC/NFOEC, Los Angeles, 2012), PDP5D.9.
P. Duan, O. Raz, B. E. Smalbrugge, J. Duis, and H. J. S. Dorren, “Chip-to-chip interconnects based on 3D stacking of opto-electrical dies on Si, ” in the Proc. SPIE. 8267, Optoelectronic Interconnects XII, 82670U (San Francisco, 2012).

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