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Hybrid optoelectronic buffer using CMOS memory and optical interfaces for 10-Gbit/s asynchronous variable-length optical packets |
Optics Express, Vol. 18, Issue 20, pp. 20565-20571 (2010)
http://dx.doi.org/10.1364/OE.18.020565
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Abstract
A hybrid optoelectronic buffer consisting of a complementary metal–oxide–semiconductor (CMOS) memory and optical/optoelectronic interface devices is described. The interface devices: an all-optical serial-to-parallel converter (SPC), electrical-to-optical parallel-to-serial converter (PSC), and optical clock pulse-train generator (OCPTG) enable write-in/read-out of preamble-free asynchronous high-speed optical packets to/from CMOS memory, and consequently, flexible and highly functional processing of the packets with CMOS circuitry. A prototype hybrid optoelectronic buffer subsystem using a field programmable gate array (FPGA)-based memory and modules for the interface devices is developed and error-free write-in and read-out operation for 10-Gbit/s asynchronous variable-length optical packets is demonstrated.
© 2010 OSA
OCIS Codes
(060.1810) Fiber optics and optical communications : Buffers, couplers, routers, switches, and multiplexers
(060.4510) Fiber optics and optical communications : Optical communications
(230.1150) Optical devices : All-optical devices
(250.3140) Optoelectronics : Integrated optoelectronic circuits
(060.6719) Fiber optics and optical communications : Switching, packet
ToC Category:
Fiber Optics and Optical Communications
History
Original Manuscript: May 20, 2010
Revised Manuscript: July 31, 2010
Manuscript Accepted: August 6, 2010
Published: September 14, 2010
Citation
Tatsushi Nakahara, Hirokazu Takenouchi, Ryohei Urata, Hiroshi Yamazaki, and Ryo Takahashi, "Hybrid optoelectronic buffer using CMOS memory and optical interfaces for 10-Gbit/s asynchronous variable-length optical packets," Opt. Express 18, 20565-20571 (2010)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-18-20-20565
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References
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