Optics InfoBase > Optics Express > Volume 19 > Issue 21 > Page 20258
|
|
Five-port optical router for photonic networks-on-chipRuiqiang Ji, Lin Yang, Lei Zhang, Yonghui Tian, Jianfeng Ding, Hongtao Chen, Yangyang Lu, Ping Zhou, and Weiwei Zhu »View Author Affiliations
Ruiqiang Ji,
Lin Yang,*
Lei Zhang,
Yonghui Tian,
Jianfeng Ding,
Hongtao Chen,
Yangyang Lu,
Ping Zhou,
and Weiwei Zhu
Optoelectronic System Laboratory, Institute of Semiconductors, Chinese Academy of Sciences, P. O. Box 912, Beijing 100083, China *Corresponding author: oip@semi.ac.cn |
Optics Express, Vol. 19, Issue 21, pp. 20258-20268 (2011)
http://dx.doi.org/10.1364/OE.19.020258
View Full Text Article
Enhanced HTML
Acrobat PDF (2104 KB)
Abstract
We experimentally demonstrate a spatially non-blocking five-port optical router, which is based on microring resonators tuned through the thermo-optic effect. The characteristics of the microring-resonator-based switching element are investigated to achieve balanced performances in its two output ports. The optical router is fabricated on the SOI platform using standard CMOS processing. The effective footprint of the device is about 440×660 μm2. The microring resonators have 3-dB bandwidths of larger than 0.31 nm (38 GHz), and extinction ratios of better than 21 dB for through ports and 16 dB for drop ports. Finally, 12.5 Gbps high-speed signal transmission experiments verify the routing functionality of the optical router.
© 2011 OSA
OCIS Codes
(130.0130) Integrated optics : Integrated optics
(230.5750) Optical devices : Resonators
(250.5300) Optoelectronics : Photonic integrated circuits
(130.4815) Integrated optics : Optical switching devices
ToC Category:
Integrated Optics
History
Original Manuscript: August 3, 2011
Revised Manuscript: September 21, 2011
Manuscript Accepted: September 22, 2011
Published: September 30, 2011
Citation
Ruiqiang Ji, Lin Yang, Lei Zhang, Yonghui Tian, Jianfeng Ding, Hongtao Chen, Yangyang Lu, Ping Zhou, and Weiwei Zhu, "Five-port optical router for photonic networks-on-chip," Opt. Express 19, 20258-20268 (2011)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-19-21-20258
Sort: Author | Year | Journal | Reset
References
- R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE96(2), 230–247 (2008). [CrossRef]
- D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE97(7), 1166–1185 (2009). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- H. X. Gu, K. H. Mo, J. Xu, and W. Zhang, “A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip,” 2009 IEEE Computer Society Annual Symposium on VlSI, 19–24 (2009).
- N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4×4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express16(20), 15915–15922 (2008). [CrossRef] [PubMed]
- M. Yang, W. M. J. Green, S. Assefa, J. Van Campenhout, B. G. Lee, C. V. Jahnes, F. E. Doany, C. L. Schow, J. A. Kash, and Y. A. Vlasov, “Non-blocking 4×4 electro-optic silicon switch for on-chip photonic networks,” Opt. Express19(1), 47–54 (2011). [CrossRef] [PubMed]
- R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express19(20), 18945–18955 (2011). [CrossRef]
- A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput.57(9), 1246–1260 (2008). [CrossRef]
- A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE97(7), 1216–1238 (2009). [CrossRef]
- C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic, “Building manycore processor-to-DRAM networks with monolithic silicon photonics,” High-Performance Interconnects, Symposium on, pp. 21–30, 16th IEEE Symposium on High Performance Interconnects, 2008.
- H. X. Gu, J. Xu, and W. Zhang, “A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip,” Design, Automation & Test in Europe Conference & Exhibition, 3–8 (2009).
- A. Joshi, C. Batten, Y. J. Kwon, S. Beamer, I. Shamim, K. Asanovic, and V. Stojanovic, “Silicon-photonic clos networks for global on-chip communication,” 2009 3rd Acm/Ieee International Symposium on Networks-on-Chip, 124–133 (2009).
- S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits43(1), 29–41 (2008). [CrossRef]
- D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro27(5), 15–31 (2007). [CrossRef]
- A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett.22(15), 1081–1083 (2010). [CrossRef]
- Y. Xie, N. Mahdi, J. Xu, W. Zhang, Q. Li, X. Wu, Y. Ye, X. Wang, and W. Liu, “Crosstalk noise and bit error rate analysis for optical network-on-chip,” 47th ACM/EDAC/IEEE Design Automation Conference, 657–660 (2010).
- L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett.35(10), 1620–1622 (2010). [CrossRef] [PubMed]
- T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys.43(2), 646–647 (2004). [CrossRef]
- L. Y. M. Tobing, P. Dumon, R. Baets, and M. K. Chin, “Boxlike filter response based on complementary photonic bandgaps in two-dimensional microresonator arrays,” Opt. Lett.33(21), 2512–2514 (2008). [CrossRef] [PubMed]
- D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro27(5), 15–31 (2007). [CrossRef]
- T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys.43(2), 646–647 (2004). [CrossRef]
- D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro27(5), 15–31 (2007). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE96(2), 230–247 (2008). [CrossRef]
- N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4×4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express16(20), 15915–15922 (2008). [CrossRef] [PubMed]
- A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput.57(9), 1246–1260 (2008). [CrossRef]
- A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett.22(15), 1081–1083 (2010). [CrossRef]
- S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits43(1), 29–41 (2008). [CrossRef]
- S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits43(1), 29–41 (2008). [CrossRef]
- D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro27(5), 15–31 (2007). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput.57(9), 1246–1260 (2008). [CrossRef]
- R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express19(20), 18945–18955 (2011). [CrossRef]
- A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE97(7), 1216–1238 (2009). [CrossRef]
- A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett.22(15), 1081–1083 (2010). [CrossRef]
- S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits43(1), 29–41 (2008). [CrossRef]
- D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro27(5), 15–31 (2007). [CrossRef]
- S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits43(1), 29–41 (2008). [CrossRef]
- S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits43(1), 29–41 (2008). [CrossRef]
- T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys.43(2), 646–647 (2004). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett.22(15), 1081–1083 (2010). [CrossRef]
- A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett.22(15), 1081–1083 (2010). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro27(5), 15–31 (2007). [CrossRef]
- T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys.43(2), 646–647 (2004). [CrossRef]
- D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro27(5), 15–31 (2007). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits43(1), 29–41 (2008). [CrossRef]
- S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits43(1), 29–41 (2008). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits43(1), 29–41 (2008). [CrossRef]
- S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits43(1), 29–41 (2008). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE96(2), 230–247 (2008). [CrossRef]
- M. Yang, W. M. J. Green, S. Assefa, J. Van Campenhout, B. G. Lee, C. V. Jahnes, F. E. Doany, C. L. Schow, J. A. Kash, and Y. A. Vlasov, “Non-blocking 4×4 electro-optic silicon switch for on-chip photonic networks,” Opt. Express19(1), 47–54 (2011). [CrossRef] [PubMed]
- N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4×4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express16(20), 15915–15922 (2008). [CrossRef] [PubMed]
- A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE97(7), 1216–1238 (2009). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro27(5), 15–31 (2007). [CrossRef]
- D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro27(5), 15–31 (2007). [CrossRef]
- D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE97(7), 1166–1185 (2009). [CrossRef]
- A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett.22(15), 1081–1083 (2010). [CrossRef]
- T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys.43(2), 646–647 (2004). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett.22(15), 1081–1083 (2010). [CrossRef]
- A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE97(7), 1216–1238 (2009). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro27(5), 15–31 (2007). [CrossRef]
- S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits43(1), 29–41 (2008). [CrossRef]
- S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits43(1), 29–41 (2008). [CrossRef]
- A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput.57(9), 1246–1260 (2008). [CrossRef]
- S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits43(1), 29–41 (2008). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE96(2), 230–247 (2008). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits43(1), 29–41 (2008). [CrossRef]
- S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits43(1), 29–41 (2008). [CrossRef]
- R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE96(2), 230–247 (2008). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro27(5), 15–31 (2007). [CrossRef]
- R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE96(2), 230–247 (2008). [CrossRef]
- S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits43(1), 29–41 (2008). [CrossRef]
- A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE97(7), 1216–1238 (2009). [CrossRef]
- R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express19(20), 18945–18955 (2011). [CrossRef]
- L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett.35(10), 1620–1622 (2010). [CrossRef] [PubMed]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express19(20), 18945–18955 (2011). [CrossRef]
- L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett.35(10), 1620–1622 (2010). [CrossRef] [PubMed]
- R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express19(20), 18945–18955 (2011). [CrossRef]
- L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett.35(10), 1620–1622 (2010). [CrossRef] [PubMed]
IEEE J. Solid-state Circuits
- S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits43(1), 29–41 (2008). [CrossRef]
IEEE Micro
- D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro27(5), 15–31 (2007). [CrossRef]
IEEE Photon. Technol. Lett.
- A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett.22(15), 1081–1083 (2010). [CrossRef]
IEEE Trans. Comput.
- A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput.57(9), 1246–1260 (2008). [CrossRef]
J. Opt. Netw.
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
Jpn. J. Appl. Phys.
- T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys.43(2), 646–647 (2004). [CrossRef]
Opt. Express
- N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4×4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express16(20), 15915–15922 (2008). [CrossRef] [PubMed]
- M. Yang, W. M. J. Green, S. Assefa, J. Van Campenhout, B. G. Lee, C. V. Jahnes, F. E. Doany, C. L. Schow, J. A. Kash, and Y. A. Vlasov, “Non-blocking 4×4 electro-optic silicon switch for on-chip photonic networks,” Opt. Express19(1), 47–54 (2011). [CrossRef] [PubMed]
- R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express19(20), 18945–18955 (2011). [CrossRef]
Opt. Lett.
- L. Y. M. Tobing, P. Dumon, R. Baets, and M. K. Chin, “Boxlike filter response based on complementary photonic bandgaps in two-dimensional microresonator arrays,” Opt. Lett.33(21), 2512–2514 (2008). [CrossRef] [PubMed]
- L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett.35(10), 1620–1622 (2010). [CrossRef] [PubMed]
Proc. IEEE
- R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE96(2), 230–247 (2008). [CrossRef]
- D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE97(7), 1166–1185 (2009). [CrossRef]
- A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE97(7), 1216–1238 (2009). [CrossRef]
Other
- C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic, “Building manycore processor-to-DRAM networks with monolithic silicon photonics,” High-Performance Interconnects, Symposium on, pp. 21–30, 16th IEEE Symposium on High Performance Interconnects, 2008.
- H. X. Gu, J. Xu, and W. Zhang, “A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip,” Design, Automation & Test in Europe Conference & Exhibition, 3–8 (2009).
- A. Joshi, C. Batten, Y. J. Kwon, S. Beamer, I. Shamim, K. Asanovic, and V. Stojanovic, “Silicon-photonic clos networks for global on-chip communication,” 2009 3rd Acm/Ieee International Symposium on Networks-on-Chip, 124–133 (2009).
- H. X. Gu, K. H. Mo, J. Xu, and W. Zhang, “A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip,” 2009 IEEE Computer Society Annual Symposium on VlSI, 19–24 (2009).
- Y. Xie, N. Mahdi, J. Xu, W. Zhang, Q. Li, X. Wu, Y. Ye, X. Wang, and W. Liu, “Crosstalk noise and bit error rate analysis for optical network-on-chip,” 47th ACM/EDAC/IEEE Design Automation Conference, 657–660 (2010).
2011, Yang, Opt. Express
- A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett.22(15), 1081–1083 (2010). [CrossRef]
- A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE97(7), 1216–1238 (2009). [CrossRef]
- D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE97(7), 1166–1185 (2009). [CrossRef]
- R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE96(2), 230–247 (2008). [CrossRef]
- S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits43(1), 29–41 (2008). [CrossRef]
- A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput.57(9), 1246–1260 (2008). [CrossRef]
- D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro27(5), 15–31 (2007). [CrossRef]
- T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw.6(1), 63–73 (2007). [CrossRef]
- T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys.43(2), 646–647 (2004). [CrossRef]
Cited By |
OSA is able to provide readers links to articles that cite this paper by participating in CrossRef's Cited-By Linking service. CrossRef includes content from more than 3000 publishers and societies. In addition to listing OSA journal articles that cite this paper, citing articles from other participating publishers will also be listed.
Related Journal Articles 
- Air-trench splitters for ultra-compact ring resonators in low refractive index contrast waveguides (OE)
- Simultaneous implementation of XOR and XNOR operations using a directed logic circuit based on two microring resonators (OE)
- Microring-resonator-based four-port optical router for photonic networks-on-chip (OE)
- Electro-optic directed logic circuit based on microring resonators for XOR/XNOR operations (OE)
- Electro-optic directed AND/NAND logic circuit based on two parallel microring resonators (OE)
Related Conference Papers 
- Diffractionless optical micro-circuitry in an inverse opal photonic band gap heterostructure
- Optical Multi-Level Logic on a Silicon Chip
- Photonic Integrated Devices for Fast Switching
- The World’s First InP 8x8 Monolithic Tunable Optical Router (MOTOR) Operating at 40 Gbps Line Rate per Port
- The World’s First InP 8x8 Monolithic Tunable Optical Router (MOTOR) Operating at 40 Gbps Line Rate per Port
- Monolithically Integrated Wavelength-Routing Switch with Double-Ring-Resonator-Coupled Tunable Lasers
- Firefox 11+
- Google Chrome 17+
- Internet Explorer 9+
- Safari 5+




OSA is a member of 