## Optics inspired logic architecture

Optics Express, Vol. 15, Issue 1, pp. 150-165 (2007)

http://dx.doi.org/10.1364/OE.15.000150

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### Abstract

Conventional architectures for the implementation of Boolean logic are based on a network of bistable elements assembled to realize cascades of simple Boolean logic gates. Since each such gate has two input signals and only one output signal, such architectures are fundamentally dissipative in information and energy. Their serial nature also induces a latency in the processing time. In this paper we present a new, principally non-dissipative digital logic architecture which mitigates the above impediments. Unlike traditional computing architectures, the proposed architecture involves a distributed and parallel input scheme where logical functions are evaluated at the speed of light. The system is based on digital logic vectors rather than the Boolean scalars of electronic logic. The architecture employs a novel conception of cascading which utilizes the strengths of both optics and electronics while avoiding their weaknesses. It is inherently non-dissipative, respects the linear nature of interactions in pure optics, and harnesses the control advantages of electrons without reducing the speed advantages of optics. This new logic paradigm was specially developed with optical implementation in mind. However, it is suitable for other implementations as well, including conventional electronic devices.

© 2007 Optical Society of America

## 1. Introduction

*et al*. and VanderLugt.

^{1, 2}These coherent processors exploited the main attributes of optics, namely its massive parallelism and speed. In particular, the success of the VanderLugt correlator raised much interest and extended applications were anticipated. As a result, intensive research efforts were started and they continued for about two decades. Unfortunately, the attributes of optics were compensated by severe technical difficulties, the lack of proper devices and their inflexibility. Consequently, researchers turned toward digital computing and attempted to replace electrons by photons, an approach which was doomed due to the fundamental differences between the behavior of light and electrons.

^{3}this attribute alone is an adequate incentive to pursue optical signal processing. Optical Fredkin gates and gate-arrays

^{4–7}were also introduced within the effort to exploit the non-dissipative nature of processing with light.

## 2. Directed logic: an Overview

*P*) is the identity operation, it’s output is the same as it’s input. Switch (hereafter

*S*) reverses its input vector. Thus

*S*(1,0) = P(0,1) = (0,1),

*S*(0,1) =

*P*(1,0) = (1,0) and

*S*(0,0) =

*P*(0,0) = (0,0). If we interpret (1,0) as “True” and (0,1) and “False”, then sequences of S and P can be used to calculate certain Boolean functions on given arguments. Trivially, S calculates Boolean negation and P calculates Boolean identity. Less trivially, we can compute Boolean XOR and XNOR with a string of S and P elements as illustrated in Figure 1 and described in the following paragraph.

*XOR*(

*v*

_{1},

*v*

_{2},…,

*v*). This is computed by the string of elements

_{n}*E*

_{1},

*E*

_{2},…

*E*where

_{n}*E*is P if

_{i}*v*= 0 and

_{i}*S*if

*v*= 1. Importantly, this means that the nature of each element is determined by the value of the corresponding variable. In Figure 1 this control is represented as a separate input at the top of each element.

_{i}*E*

_{1}receives the input (1,0) and thereafter the output of each element is the input to the next.

*A*= 0.) If these were true Boolean values, this would amount to a violation of the law of excluded middle.

### 2.1. Directed logic and Fredkin Gates

^{4,9}require that the gates be controlled by a signal which is different in character from the other inputs. In most cases the control signal is electronic. However, even in ‘all optical’ solutions the controlling signal differs from the other inputs, for example by being of a different wavelength. This difference means that optical Fredkin gates have not been cascadeable in the way that Fredkin envisaged. This in turn has meant that they cannot be shown to produce all of Boolean logic. We resolve this problem by reinventing cascading.

### 2.2. Directed logic cascading

#### 2.2.1. From syntax to circuits

*p*OR

*q*’ is in infix notation while ‘

*pq*OR’ is in suffix notation.

#### 2.2.2. Building a complex circuit

*A*OR

*B*) AND

*C*. The circuit for (

*A*OR

*B*) AND

*C*is obtained by inserting circuits for

*A*OR

*B*into the

*A*and

*A*′ argument places of the circuit for AND as indicated in Fig. 3. The end result of the nesting is shown in Figure 4.

*A*OR

*B*) AND

*C*is equivalent to

*C*AND (

*A*OR

*B*) and then reading the circuit off of the latter formula. The result is shown in Figure 5. Moreover, if we are not interested in the complement output, a significant fraction of the circuit can be discarded (i.e. the right hand decomputing OR gate in Fig. 4).

## 3. Advantages and limitations of directed logic

### 3.1. Slower is Faster

^{5}level of logic in a clock period of 1/3 nanosecond. This represents a factor of about 10

^{4}over current logic implementations.

### 3.2. Conservative and Reversible

^{1112}and

^{13}) DL makes no claim to being the best or most complete implementation of conservative logic. Indeed, our primary point is simply that DL is an optically implementable logic, something that has been hard to come by. The fact that it is conservative is an added bonus.

### 3.3. Two limitations

#### 3.3.1. Fan-out

#### 3.3.2. Sequential Logic

## 4. Toward optical implementation

### 4.1. Optical controlled switches: an updated survey

#### 4.1.1. Polarization switching gate

#### 4.1.2. Acousto-optic gate

#### 4.1.3. Photorefractive gate

#### 4.1.4. Waveguide coupler gates

#### 4.1.5. Mach-Zehnder gates

### 4.2. Advanced network implementations

#### 4.2.1. Amplification

#### 4.2.2. Parallel addressing and smart pixels

#### 4.2.3. Systolic process

## 5. Prospects for the Future

### 5.1. Scaling with Technology

^{4,15}and as optical technology advances, we expect ever faster, smaller mini-optics, and more energy efficient Fredkin gates to appear. Because the current proposal is based on a re-envisioning of the logical paradigm, these new technologies may be seamlessly incorporated in much the way that improved transistors have been incorporated in electronic logic.

### 5.2. 2-D Multi-channel computation

^{5}to form a multichannel computing system for highly parallel computation.

### 5.3. Beyond logic operations

## 6. Conclusion

## Appendix A: List of Boolean circuits

## Acknowledgments

## References and links

1. | L. J. Cutrona, E. N. Leith, C. J. Palermo, and L. J. Porcello, “Optical data processing and filtering systems,” IRE Trans. Inform. Theory |

2. | A. B. VanderLugt, “Optical data processing and filtering systems,” IRE Trans. Inform. Theory |

3. | H. J. Caulfield and J. Shamir, “Wave-particle duality processors – characteristics, requirements and applications,” J. Opt. Soc. Am. |

4. | J. Shamir, H. J. Caulfield, W. Micelli, and R. J. Seymour, “Optical Computing and the Fredkin Gates,” Applied Optics |

5. | J. Shamir, “Three-dimensional optical interconnection gate array,” Appl. Opt. |

6. | M. M. Mirsalehi, J. Shamir, and H. J. Caulfield, “Residue arithmetic processing utilizing optical Fredkin gate arrays,” Appl. Opt. |

7. | K. M. Johnson, M. Surette, and J. Shamir, “Optical interconnection network using polarization-based ferroelectric liquid crystal gates,” Appl. Opt. |

8. | E. Fredkin and T. Toffoli, “Conservative Logic,” International Journal of Theoreticl Physics |

9. | H. J. Caulfied, R. A. Soref, L. Qian, A. Zavalin, and J. Hardy, “Generalized Optical Logic Elements – GOLEs,” under review . |

10. | R. Landauer, “Irreversibility and Heat Generation in the Computing Process,” IBM Journal of Research and Development |

11. | S. Younis, “Asymptotically zero energy computing using split-level charge recovery logic,” Ph.D. thesis , MIT (1994). |

12. | S. Younis and T. Knight, “Asymptotically zero energy split-level charge recovery logic,” in |

13. | M. P. Frank, “Physical Limits of Computing. Lecture #24 Adiabatic CMOS,” (2002). URL http://www.cise.ufl.edu/mpf/physlim/PhysLimL24.ppt. |

14. | A. I. Zavalin, J. Shamir, C. S. Vikram, and H. J. Caulfield, “Achieving stabilization in interferometric logic operations,” Appl. Opt. |

15. | H. J. Caulfied and R. A. Soref, “Universal reconfigurable optical logic with silicon-on-insulator resonant structures,” Photonics and Nanostructures - Fundamentals and Applications (to appear). |

**OCIS Codes**

(200.3760) Optics in computing : Logic-based optical processing

(200.4660) Optics in computing : Optical logic

(200.4740) Optics in computing : Optical processing

**ToC Category:**

Optical Computing

**History**

Original Manuscript: August 28, 2006

Revised Manuscript: December 4, 2006

Manuscript Accepted: December 4, 2006

Published: January 8, 2007

**Citation**

James Hardy and Joseph Shamir, "Optics inspired logic architecture," Opt. Express **15**, 150-165 (2007)

http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-15-1-150

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### References

- L. J. Cutrona, E. N. Leith, C. J. Palermo, and L. J. Porcello, "Optical data processing and filtering systems," IRE Trans. Inf. Theory IT-6, 386-400 (1960). [CrossRef]
- A. B. VanderLugt, "Optical data processing and filtering systems," IRE Trans. Inf. Theory IT-10, 139-145 (1964).
- H. J. Caulfield and J. Shamir, "Wave-particle duality processors - characteristics, requirements and applications," J. Opt. Soc. Am. A 7, 1314-1323 (1990). [CrossRef]
- J. Shamir, H. J. Caulfield, W. Micelli, and R. J. Seymour, "Optical Computing and the Fredkin Gates," Appl. Opt. 25, 1604-1607 (1986). [CrossRef]
- J. Shamir, "Three-dimensional optical interconnection gate array," Appl. Opt. 26, 3455-3457 (1987). [CrossRef] [PubMed]
- M. M. Mirsalehi, J. Shamir, and H. J. Caulfield, "Residue arithmetic processing utilizing optical Fredkin gate arrays," Appl. Opt. 26, 3940-3946 (1987). [CrossRef] [PubMed]
- K. M. Johnson, M. Surette, and J. Shamir, "Optical interconnection network using polarization-based ferroelectric liquid crystal gates," Appl. Opt. 27, 1727-1733 (1988). [CrossRef] [PubMed]
- E. Fredkin and T. Toffoli, "Conservative Logic," Int. J. Theor. Phys. 21, 219-253 (1982). [CrossRef]
- H. J. Caulfied, R. A. Soref, L. Qian, A. Zavalin, and J. Hardy, "Generalized Optical Logic Elements - GOLEs," under review.
- R. Landauer, "Irreversibility and heat generation in the computing process," IBM J. Res. Dev. 5, 183-191 (1961). [CrossRef]
- S. Younis, "Asymptotically zero energy computing using split-level charge recovery logic," Ph.D. thesis, MIT (1994).
- S. Younis and T. Knight, "Asymptotically zero energy split-level charge recovery logic," in Proc. of 1994 International Workshop on Low Power Design, pp. 177-182 (1994).
- M. P. Frank, "Physical limits of computing. Lecture #24 Adiabatic CMOS," (2002). URL http://www.cise.ufl.edu/mpf/physlim/PhysLimL24.ppt.
- A. I. Zavalin, J. Shamir, C. S. Vikram, and H. J. Caulfield, "Achieving stabilization in interferometric logic operations," Appl. Opt. 45(2), 360-365 (2006). [CrossRef]
- H. J. Caulfied and R. A. Soref, "Universal reconfigurable optical logic with silicon-on-insulator resonant structures," Photonics Nanostruct. Fundam. Appl. (to appear).

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