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Optics Express

Optics Express

  • Editor: C. Martijn de Sterke
  • Vol. 15, Iss. 20 — Oct. 1, 2007
  • pp: 12686–12691
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Multilayer 3-D photonics in silicon

Prakash Koonath and Bahram Jalali  »View Author Affiliations


Optics Express, Vol. 15, Issue 20, pp. 12686-12691 (2007)
http://dx.doi.org/10.1364/OE.15.012686


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Abstract

Three-dimensionally (3-D) integrated photonic structures in multiple layers of silicon are reported. Implantation of oxygen ions into a silicon-on-insulator substrate with a patterned thermal oxide mask, followed by a high temperature anneal, creates photonic structures on 3-D integrated layers of silicon. This process is combined with epitaxial growth to achieve devices on three vertically integrated layers of silicon. As a demonstration vehicle, we report a multistage optical filter that comprises of coupled microdisks on two subsurface silicon layers with bus waveguides on the surface (3rd) layer. The optical filter shows extinction ratios in excess of 14 dB, with excess insertion loss of less than 1 dB.

© 2007 Optical Society of America

1. Introduction

Recent advances in silicon based photonics [1–12

1. O. Boyraz and B. Jalali, “Demonstration of a Silicon Raman Laser,” Opt. Express 12, 5269–5273 (2004). [CrossRef] [PubMed]

] have brought the much anticipated integration of photonics and electronics closer to reality. Transistor size continues to shrink — a trend that is fueled by the economic benefit gained when a larger number of circuits are obtained from a single silicon wafer. While today’s electronic chips boast critical dimensions of 35 nm [13

13. S. Tyagi, et al. “A 65nm ultra low power logic platform technology using Uni-axial strained silicon transistors,” IEEE IEDM Tech. Digest 245–247 (2005). [CrossRef]

], the dimensions of optical waveguides have a hard lower limit of more than 200 nm, set by the optical wavelength in silicon [14

14. T. Tsuchizawa, et al., “Microphotonics devices based on silicon microfabrication technology,” EEE J. Sel. Top. Quantum Electron. 11, 232–240 (2005). [CrossRef]

,15

15. Y. A. Vlasov and S. J. McNab, “Losses in single-mode silicon-on-insulator strip waveguides and bends,” Opt. Express 21, 1622–1631 (2004). [CrossRef]

]. These differences together with the high premium on the silicon real estate [16

16. A. Fazio, “A high density high performance 180nm generation EtoxTM flash memory technology,” IEEE IEDM Tech. Digest 267–270 (1999).

] serve as motivation for technologies that facilitate the integration photonics on a silicon chip in a real estate efficient three-dimensional (3-D) manner [17

17. W. R. Davis, et al., “Demystifying 3D ICs: The pros and cons of going vertical,” IEEE Design and Test of Computers 22, 498–510 (2005). [CrossRef]

]. Here we demonstrate a Complimentary Metal Oxide Semiconductor (CMOS) compatible technology that features devices on 3 vertically stacked device layers.

2. Fabrication of multilayer structures

Devices on multiple layers are fabricated using a technique called the SIMOX (Separation by IMplantation of OXygen) 3-D sculpting [18

18. P. Koonath, K. Kishima, T. Indukuri, and B. Jalali, “Sculpting of three-dimensional nano-optical structures in silicon,” Appl. Phys. Letts. 83, 4909–4911 (2003). [CrossRef]

], a modified form of the conventional SIMOX process. The SIMOX process is conventionally used to obtain thin silicon layers (∼ 3000Å) on top of a buried oxide layer of thickness of the same order of magnitude, to produce high quality silicon-on-insulator (SOI) substrates [19–20

19. M. Chen, et. al, “Dose-energy match for the formation of high-integrity buried oxide layers in low-dose separation-by-implantation-of-oxygen materials,” Appl. Phys. Letts. 80, 880–82 (2002). [CrossRef]

].

Fig. 1. Schematic of the process flow for the fabrication of multilayer structures using SIMOX 3-D sculpting. (a) Starting SOI wafer, with a semitransparent silicon oxide mask on it, is implanted with oxygen ions. (b) High temperature anneal after the implantation results in the formation of a continuous buried oxide layer. (c) Epitaxial growth of silicon. (d) Silicon dioxide is grown thermally and patterned using photolithography to create a semitransparent oxide mask. This wafer then undergoes oxygen ion implantation as in step a. (e) High temperature annealing results in the realization of the second layer of sub-surface waveguides separated from a surface silicon layer. (f) Photolithography and reactive ion etching performed on the surface silicon layer to create devices on the surface silicon layer.

Figure 1 depicts the process flow for creating multilayer structures. Implantation of oxygen ions is performed on an SOI substrate that has been patterned with thermally grown oxide. The semi-transparent thermal oxide mask produces a difference in the penetration depth of the oxygen ions between regions with and without thermal oxide, as they traverse the substrate. A high temperature anneal (∼ 1300°C) after the implantation cures the damage created on the silicon crystal due to the implantation process. It also aids the formation of a continuous layer of silicon dioxide. This leads to the formation of sub-surface waveguide structures separated from a surface silicon layer by the silicon dioxide layer formed as a result of the oxygen implantation and anneal. This surface silicon layer is used as the seed layer to grow silicon epitaxially on the substrate. After the epitaxial growth, the substrate goes through another set of implantation and annealing steps, resulting in the formation of a second layer of buried devices and a surface silicon layer. Photonic or electronic devices may be defined on the surface silicon layer using conventional lithography and etching process, resulting in the realization of three layers of 3-D integrated devices. There has been an attempt previously to fabricate multilayer 3-D structures in SOI wafers using the SIMOX process, combining it with epitaxial growth of Silicon [21

21. R. A. Soref, F. Namavar, E. Cortesi, L. Friedman, and R. Lareau, “Vertical 3D integration of silicon waveguides in a Si-SiO2-Si-SiO2-Si structure,” Proc SPIE 1389, 408–421 (1990). [CrossRef]

]. The complete process involved two implantation steps and two epitaxial growths in order to grow vertically integrated SOI waveguides. The waveguides fabricated in this case were planar in nature with a guiding layer thickness of 2 microns.

Figure 2 shows the cross sectional SEM pictures of rib waveguides realized in the three vertically stacked layers of silicon. It is very clear that the process of SIMOX 3-D sculpting has successfully been employed to realize multilayer nanophotonic structures in silicon.

Fig. 2. Cross-sectional Scanning Electron Microscope (SEM) pictures of devices fabricated in a multilayer structure. a) Sub-surface waveguides in the first layer of the structure after oxygen implantation and high temperature anneal. Two layers of silicon are seen above the waveguide structure.b) Sub- surface waveguides in the second layer of the structure. A layer of silicon above and another layer of silicon below the waveguides in this layer are also seen.c) Rib waveguides in the surface silicon realized by photolithography and etching. Two layers of silicon below this surface layer are also seen in the picture.

It may be seen from Fig. 2(b) that the oxide layer that defines the second layer of buried devices is discontinuous. This is due to the fact that the amount of oxygen ion dose that entered the wafer is less than the optimum value of 5×1017 ions per cm2 required for the formation of a continuous oxide layer. This can be verified by measuring the thickness of the second buried oxide layer that was formed, which is around 85 nm. For a dose of 5×1017 ions per cm2, the thickness of a stoichiometric oxide layer is expected to be around 115 nm, as is measured in the case of the oxide layer formed in the first implantation step. We surmise that the difference in the dose that penetrated the wafer during the second implantation step must arise from the process variations at the commercial implantation facility where the implantation was performed. By ensuring the presence of optimum dose inside the substrate, a continuous layer of oxide can be realized. It needs to be mentioned here that, even though the oxide layer is discontinuous, finite element method based simulations show that the structure supports guided optical modes. Figure 3 depicts the electric field profile of the fundamental mode of the rib waveguides formed in the second silicon layer. The 2 μm wide waveguides fabricated in this case are multimode in nature. However, by choosing the input coupling conditions appropriately to launch the fundamental mode, it is possible to avoid the excitation of higher order modes that might affect the performance of the filter.

Fig. 3. The electric field profile of the fundamental mode of a waveguide in the second silicon layer. a) Fundamental mode field profile of the waveguides defined in the second silicon layer, calculated using a finite element mode solver. b) Waveguide structure used for the simulation results shown in part a, which closely matches the experimentally observed structure, with a discontinuous oxide layer, shown in Fig. 2.

It may be noted that the approach used here to realize multilayer 3D photonic structures differs from that of [22

22. L. C. Kimerling, et.al, “Electronic-Photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 612502–1–10 (2006). [CrossRef]

] where deposition of nanocrystalline silicon upon oxidized SOI was used to form a surface guiding layer in a 3D silicon photonic structure. In [22

22. L. C. Kimerling, et.al, “Electronic-Photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 612502–1–10 (2006). [CrossRef]

], there is one guiding layer which is situated on the surface, in contrast to the present work where there are three different guiding layers that are evanescently coupled to each other. Also, the SIMOX process used in the present work preserves the crystalline nature of the surface silicon, thereby making it possible to realize CMOS devices on this surface layer, as has been demonstrated previously [23

23. T. Indukuri, P. Koonath, and B. Jalali, “Three-dimensional integration of metal-oxide-semiconductor transistor with subterranean photonics in silicon,” Appl. Phys. Lett. 88, 121108 (2006). [CrossRef]

].

3. Multilayer 3-D photonic devices

As a vehicle for the proof of concept, an optical filter was fabricated by cascading multiple microcavities, the schematic of which is shown in Fig. 4(a). Here, the microresonators are realized in the two buried layers of silicon that are coupled to each other and to the bus waveguides fabricated on the surface silicon layer through intervening oxide layers (the intervening layer of oxide through which the evanescent coupling of light takes place is omitted in Fig. 4(a) for the simplicity of illustration). Figure 4(b) shows the optical micrograph of the top view of the fabricated device with the arrows indicating the direction of flow of optical energy through these devices. The microdisks have a radius of 20 μm, and the bus waveguides have a width of 2 μm. When optical energy is introduced to the input port of the device, resonant wavelengths are transmitted to the drop port, after traversing through vertically coupled silicon layers. The complete path of the optical field (from the input bus waveguide to the output drop port waveguide) includes five layers of silicon and four evanescent coupling stages.

Fig. 4 Three-dimensionally integrated microcavity structures in multilayer silicon structure. a) Schematic of the three-dimensionally coupled microcavities realized using SIMOX 3-D sculpting, where the blue features represent silicon. Microdisk resonators are realized in two sub-surface silicon layers that are coupled to each other and to bus waveguides fabricated on the surface silicon layer. b) The optical micrograph of the top view of the fabricated device where the arrows indicate the direction of flow of optical energy through the multilayer structure. Resonant wavelengths are transmitted to the drop port after traversing through the vertically coupled silicon layer structure. Non-resonant wavelengths appear at the thru port.

The spectral characteristics of the filter at the drop port of the filter were measured by launching the optical power from an Amplified Spontaneous Emission (ASE) source at the input port of the device and collecting the optical spectra at the drop port using a spectrum analyzer, the results of which are shown in Fig. 5. The distance between two consecutive resonant wavelengths, free spectral range of the device, was found to be around 5.6 nm. The extinction ratio, as measured by the ratio of the maximum power (at the resonant wavelength) to that of the minimum power (at the off-resonance wavelength) is found to have a maximum value of ∼ 14 dB in the wavelength range of measurement. The excess insertion loss of the multistage filter structure was measured to be ∼1 dB. This is done by tuning the wavelength of a laser through a resonance of the device and comparing the optical power at the thru (out of resonance) and drop (in resonance) ports of the device. The normalized spectral characteristics of the thru port are shown in Fig. 6. These results validate the capability of the SIMOX 3-D sculpting technique for fabricating complex 3-D integrated devices.

Fig. 5. Spectral characteristics of the drop port of the multistage microdisk filter device. Wavelengths that are resonant with the microdisk structure travel through the multilayer structure and get collected at the drop port of the device. Non-resonant wavelengths are collected at the thru port of the device.
Fig. 6. Spectral characteristics of the thru port of the multistage microdisk filter device. Non-resonant wavelengths are collected at the thru port of the device. By comparing with Fig. 5, it may be seen that every peak in Fig. 5 corresponds to a dip in Fig. 6.

5. Summary

A method to create photonic devices that span multiple vertically-coupled layers of silicon has been demonstrated. 3-D integration facilitates the synthesis of devices with precisely controllable coupling characteristics and can lead to efficient use of silicon real estate. The latter is realized when different layers are used for create independent devices that reside on top of each other. A particularly logical arrangement will be to confine photonics devices to the two sub-surface layers and dedicating the surface silicon layer to electronic circuits.

Acknowledgments

References and links

1.

O. Boyraz and B. Jalali, “Demonstration of a Silicon Raman Laser,” Opt. Express 12, 5269–5273 (2004). [CrossRef] [PubMed]

2.

H. Rong, et. al, “Low-threshold continuous-wave Raman silicon laser,” Nat. Photonics 1, 232 – 237 (2007). [CrossRef]

3.

Q. Xu, B. Schmidt, S. Pradhan, and M. Lipson, “Micrometre-scale silicon electro-optic modulator,” Nature 435, 325–327 (2005). [CrossRef] [PubMed]

4.

X. Chen, N. C. Panoiu, and R. M. Osgood, “Theory of Raman-mediated pulse amplification in silicon wire waveguides,” IEEE J. of Quantum Electron. 42, 160–170 (2006). [CrossRef]

5.

F. Xia, L. Sekaric, and Y. Vlasov, “Ultracompact optical buffers on a silicon chip,” Nat. Photonics 1, 65–71 (2006). [CrossRef]

6.

K. Jia, et al, “Silicon-on-insulator-based optical demultiplexer employing turning-mirror-integrated arrayed-waveguide grating,” IEEE Photon. Technol. Lett. 17, 378–380 (2005). [CrossRef]

7.

A. Polman, B. Min, J. Kalkman, T. J. Kippenberg, and K. Vahala, “Ultralow-threshold erbium-implanted toroidal microlaser on silicon,” Appl. Phys. Lett. 84, 1037–1039 (2004). [CrossRef]

8.

M. Borselli, K. Srinivasan, P. Barclay, and O. Painter, “Rayleigh scattering, mode coupling, and optical loss in silicon microdisks,” Appl. Phys. Lett. 85, 3693–3695 (2004). [CrossRef]

9.

Y. Kuo, et al, “Strong quantum-confined stark effect in germanium quantum-well structures on silicon,” Nature 437, 1334–1336 (2005). [CrossRef] [PubMed]

10.

P. Dumon, et al. “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography,” IEEE Photon. Technol. Lett. 16, 1328–1330 (2004). [CrossRef]

11.

M. Hochberg, et al., “Terahertz All-Optical Modulation in Silicon-Polymer Hybrid System,” Nat. Mater. 5, 703 – 709 (2006). [CrossRef] [PubMed]

12.

T. K. Liang and H. K. Hsang, “Role of free carriers from two-photon absorption in Raman amplification in silicon-on-insulator waveguides,” Appl. Phys. Letts. 84, 2745–2747 (2004). [CrossRef]

13.

S. Tyagi, et al. “A 65nm ultra low power logic platform technology using Uni-axial strained silicon transistors,” IEEE IEDM Tech. Digest 245–247 (2005). [CrossRef]

14.

T. Tsuchizawa, et al., “Microphotonics devices based on silicon microfabrication technology,” EEE J. Sel. Top. Quantum Electron. 11, 232–240 (2005). [CrossRef]

15.

Y. A. Vlasov and S. J. McNab, “Losses in single-mode silicon-on-insulator strip waveguides and bends,” Opt. Express 21, 1622–1631 (2004). [CrossRef]

16.

A. Fazio, “A high density high performance 180nm generation EtoxTM flash memory technology,” IEEE IEDM Tech. Digest 267–270 (1999).

17.

W. R. Davis, et al., “Demystifying 3D ICs: The pros and cons of going vertical,” IEEE Design and Test of Computers 22, 498–510 (2005). [CrossRef]

18.

P. Koonath, K. Kishima, T. Indukuri, and B. Jalali, “Sculpting of three-dimensional nano-optical structures in silicon,” Appl. Phys. Letts. 83, 4909–4911 (2003). [CrossRef]

19.

M. Chen, et. al, “Dose-energy match for the formation of high-integrity buried oxide layers in low-dose separation-by-implantation-of-oxygen materials,” Appl. Phys. Letts. 80, 880–82 (2002). [CrossRef]

20.

H. Ono and A. Ogura, “Evaulation of buried oxide formation in low dose SIMOX,” Appl. Surf. Sci. 159–160, 104–110(2000).

21.

R. A. Soref, F. Namavar, E. Cortesi, L. Friedman, and R. Lareau, “Vertical 3D integration of silicon waveguides in a Si-SiO2-Si-SiO2-Si structure,” Proc SPIE 1389, 408–421 (1990). [CrossRef]

22.

L. C. Kimerling, et.al, “Electronic-Photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 612502–1–10 (2006). [CrossRef]

23.

T. Indukuri, P. Koonath, and B. Jalali, “Three-dimensional integration of metal-oxide-semiconductor transistor with subterranean photonics in silicon,” Appl. Phys. Lett. 88, 121108 (2006). [CrossRef]

OCIS Codes
(220.4000) Optical design and fabrication : Microstructure fabrication
(130.3990) Integrated optics : Micro-optical devices

ToC Category:
Integrated Optics

History
Original Manuscript: July 9, 2007
Revised Manuscript: August 15, 2007
Manuscript Accepted: August 15, 2007
Published: September 19, 2007

Citation
Prakash Koonath and Bahram Jalali, "Multilayer 3-D photonics in silicon," Opt. Express 15, 12686-12691 (2007)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-15-20-12686


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References

  1. O. Boyraz and B. Jalali, "Demonstration of a Silicon Raman Laser," Opt. Express 12, 5269-5273 (2004). [CrossRef] [PubMed]
  2. H. Rong,  et al, "Low-threshold continuous-wave Raman silicon laser," Nat. Photonics 1, 232 - 237 (2007). [CrossRef]
  3. Q. Xu, B. Schmidt, S. Pradhan and M. Lipson, "Micrometre-scale silicon electro-optic modulator," Nature 435,325-327 (2005). [CrossRef] [PubMed]
  4. X. Chen, N. C. Panoiu, and R. M. Osgood, "Theory of Raman-mediated pulse amplification in silicon wire waveguides," IEEE J. of Quantum Electron. 42, 160-170 (2006). [CrossRef]
  5. F. Xia, L. Sekaric and Y. Vlasov, "Ultracompact optical buffers on a silicon chip," Nat. Photonics 1, 65-71 (2006). [CrossRef]
  6. K. Jia,  et al, "Silicon-on-insulator-based optical demultiplexer employing turning-mirror-integrated arrayed-waveguide grating," IEEE Photon. Technol. Lett. 17, 378-380 (2005). [CrossRef]
  7. A. Polman, B. Min, J. Kalkman, T. J. Kippenberg, and K. Vahala, "Ultralow-threshold erbium-implanted toroidal microlaser on silicon," Appl. Phys. Lett. 84, 1037-1039 (2004). [CrossRef]
  8. M. Borselli, K. Srinivasan, P. Barclay, and O. Painter, "Rayleigh scattering, mode coupling, and optical loss in silicon microdisks," Appl. Phys. Lett. 85, 3693-3695 (2004). [CrossRef]
  9. Y. Kuo,  et al, "Strong quantum-confined stark effect in germanium quantum-well structures on silicon," Nature 437, 1334-1336 (2005). [CrossRef] [PubMed]
  10. P. Dumon,  et al. "Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography," IEEE Photon. Technol. Lett. 16, 1328-1330 (2004). [CrossRef]
  11. M. Hochberg,  et al., "Terahertz All-Optical Modulation in Silicon-Polymer Hybrid System," Nat. Mater. 5, 703 - 709 (2006). [CrossRef] [PubMed]
  12. T. K. Liang and H. K. Hsang, "Role of free carriers from two-photon absorption in Raman amplification in silicon-on-insulator waveguides," Appl. Phys. Letts. 84, 2745-2747 (2004). [CrossRef]
  13. S. Tyagi,  et al. "A 65nm ultra low power logic platform technology using Uni-axial strained silicon transistors," IEEE IEDM Tech. Digest 245-247 (2005). [CrossRef]
  14. T. Tsuchizawa,  et al., "Microphotonics devices based on silicon microfabrication technology," EEE J. Sel. Top. Quantum Electron. 11, 232-240 (2005). [CrossRef]
  15. Y. A. Vlasov and S. J. McNab, "Losses in single-mode silicon-on-insulator strip waveguides and bends," Opt. Express 21, 1622-1631 (2004). [CrossRef]
  16. A. Fazio, "A high density high performance 180nm generation Etox™ flash memory technology," IEEE IEDM Tech. Digest 267-270 (1999).
  17. W. R. Davis,  et al., "Demystifying 3D ICs: The pros and cons of going vertical," IEEE Design and Test of Computers 22, 498-510 (2005). [CrossRef]
  18. P. Koonath, K. Kishima, T. Indukuri and B. Jalali, "Sculpting of three-dimensional nano-optical structures in silicon," Appl. Phys. Letts. 83, 4909-4911 (2003). [CrossRef]
  19. M. Chen,  et al, "Dose-energy match for the formation of high-integrity buried oxide layers in low-dose separation-by-implantation-of-oxygen materials," Appl. Phys. Letts. 80, 880-82 (2002). [CrossRef]
  20. H. Ono and A. Ogura, "Evaulation of buried oxide formation in low dose SIMOX," Appl. Surf. Sci. 159-160, 104-110(2000).
  21. R. A. Soref, F. Namavar, E. Cortesi, L. Friedman, and R. Lareau, "Vertical 3D integration of silicon waveguides in a Si-SiO2-Si-SiO2-Si structure," Proc SPIE 1389, 408-421 (1990). [CrossRef]
  22. L. C. Kimerling,  et al, "Electronic-Photonic integrated circuits on the CMOS platform," Proc. SPIE 6125, 612502-1-10 (2006). [CrossRef]
  23. T. Indukuri, P. Koonath, and B. Jalali, "Three-dimensional integration of metal-oxide-semiconductor transistor with subterranean photonics in silicon," Appl. Phys. Lett. 88, 121108 (2006). [CrossRef]

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