OSA's Digital Library

Optics Express

Optics Express

  • Editor: C. Martijn de Sterke
  • Vol. 17, Iss. 25 — Dec. 7, 2009
  • pp: 22680–22688
« Show journal navigation

A novel reconfigurable optical interconnect architecture using an Opto-VLSI processor and a 4-f imaging system

Mingya Shen, Feng Xiao, and Kamal Alameh  »View Author Affiliations


Optics Express, Vol. 17, Issue 25, pp. 22680-22688 (2009)
http://dx.doi.org/10.1364/OE.17.022680


View Full Text Article

Acrobat PDF (383 KB)





Browse Journals / Lookup Meetings

Browse by Journal and Year


   


Lookup Conference Papers

Close Browse Journals / Lookup Meetings

Article Tools

Share
Citations

Abstract

A novel reconfigurable optical interconnect architecture for on-board high-speed data transmission is proposed and experimentally demonstrated. The interconnect architecture is based on the use of an Opto-VLSI processor in conjunction with a 4-f imaging system to achieve reconfigurable chip-to-chip or board-to-board data communications. By reconfiguring the phase hologram of an Opto-VLSI processor, optical data generated by a vertical Cavity Surface Emitting Laser (VCSEL) associated to a chip (or a board) is arbitrarily steered to the photodetector associated to another chip (or another board). Experimental results show that the optical interconnect losses range from 5.8dB to 9.6dB, and that the maximum crosstalk level is below −36dB. The proposed architecture is tested for high-speed data transmission, and measured eye diagrams display good eye opening for data rate of up to 10Gb/s.

© 2009 OSA

1. Introduction

Among the various reported optical interconnect architectures, the free-space optical interconnect is a promising solution to achieving large bandwidth and low power consumption while keeping other advantages of low losses and EMI performances for HPC data communication links. Free-space optical interconnects enable dense and reconfigurable optical signal transmission and distribution to be realized simultaneously. A reconfigurable free space optical interconnect architecture, employing a liquid crystal on silicon (LCoS) processor in conjunction with a polarization beam splitter, has been reported [17

17. C. J. Henderson, D. G. Leyva, and T. D. Wilkinson, “Free space adaptive optical interconnect at 1.25 Gb/s with beam steering using a ferroelectric liquid-crystal SLM,” J. Lightwave Technol. 24(5), 1989–1997 ( 2006). [CrossRef]

], demonstrating an optical loss of 13.6dB and a bit error rate (BER) of 10−12 at 1.25Gb/s. Another reconfigurable optical interconnect architecture based on the use of a prism together with a lens and a spatial light modulator (SLM) has also been adopted [22

22. N. McArdle, M. Naruse, H. Toyoda, Y. Kobayashi, and M. Ishikawa, “Reconfigurable optical interconnections for parallel computing,” Proc. IEEE 88(6), 829–837 ( 2000). [CrossRef]

]. A 2.5Gb/s reconfigurable optical interconnect architecture constructed using two Opto-very-large-scale-integration (Opto-VLSI) processors has been reported, demonstrating experimentally the ability of Opto-VLSI processors to realise free-space point-to-point as well as point-to-multi-point optical interconnects [23

23. M. Aljada, K. E. Alameh, Y. T. Lee, and I. S. Chung, “High-speed (2.5 Gbps) reconfigurable inter-chip optical interconnects using opto-VLSI processors,” Opt. Express 14(15), 6823–6836 ( 2006). [CrossRef] [PubMed]

].

In this paper, we propose and experimentally demonstrate a novel fiber-based optical interconnect architecture based on the use of an Opto-VLSI processor in conjunction with a 4-f imaging system, where the input optical beams carrying data from VCSEL transmitters can be steered and arbitrarily switched to different output fiber ports (or receivers). The proposed reconfigurable optical interconnect architecture can realize chip-to-chip or board-to-board communication at data rates of up to 10Gb/s.

2. Opto-VLSI processor

The Opto-VLSI processor is a core element used in the proposed optical interconnect architecture. It consists of Very-Large-Scale-Integrated (VLSI) circuits that drive an array of liquid crystal (LC) cells [24

24. J. Stockley, and S. Serati, “Advances in liquid crystal beam steering,” Boulder Nonlinear Systems, www.bnonliner.com, (2004).

]. It can generate multi-phase holographic blazed gratings capable of steering or shaping optical beams, as illustrated in Fig. 1
Fig. 1 (a) Gray level versus pixel number of different blazed gratings; (b) Corresponding computer-generated steering phase holograms; (c) Principle of beam steering using an Opto-VLSI processor. The steering angle is inversely proportional to the blazed grating period.
. Each pixel of the Opto-VLSI processor is independently driven by a discrete voltage applied between the aluminum mirrorelectrode across the LC cells and a transparent Indium-Tin oxide (ITO) layer as the second electrode. A quarter-wave-plate (QWP) layer between the LC and the aluminum mirror is usually used to accomplish polarization-insensitive operation [25

25. K. M. Johnson, D. J. McKnight, and I. Underwood, “Smart spatial light modulators using liquid crystals on silicon,” IEEE J. Quantum Electron. 29(2), 699–714 ( 1993). [CrossRef]

].

An Opto-VLSI processor is electronically controlled, software configurable and is capable of controlling multiple optical beams simultaneously without mechanical moving parts. For an optical beam incident on an Opto-VLSI processor with a small incidence angle, the x-direction θx or the y-direction θy of the 1st-order diffraction beam is determined by the linearized grating equation [26

26. J. W. Goodman and A. M. Silvestri, “Some effects of Fourier-domain phase quantization,” IBM J. Res. Develop. 14(9), 478–484 ( 1970). [CrossRef]

]:
θx/y=λpx/y=λ(sx/y)(Nx/y)
(1)
where px/y is grating period in the x-direction or the y-direction, sx/y is the size of square or rectangular liquid crystal pixels and Nx/y is the number of the pixels in a period of the grating. The digitized phase levels, {φn}, and steering efficiency η(M) of the grating can be expressed as:
ϕn=n2πM,n=1,...,M
(2)
and
η(M)=[sin(π/M)(π/M)]2
(3)
where M is the number of discrete phase levels. Equation (1) shows that a diffracted beam can be steered to a desired direction θx/y by selecting px/y parameters i.e. sx/y and Nx/y for a certain wavelength. The steered beam intensity (or steering efficiency) is dependent on the number of discrete phase levels as shown in Eq. (3).

3. Proposed reconfigurable optical interconnect architecture

Figure 2
Fig. 2 Illustration of chip-to-chip reconfigurable optical interconnects employing 1x3 optical switches.
shows the proposed reconfigurable optical interconnect architecture. The principle of operation is illustrated through an example of a reconfigurable optical interconnect architecture providing interconnections between a set of three chips (Chips 1-3) and another set of three chips (Chips 4-6). Each chip of a set is associated with a VCSEL device that is modulated by the data generated by that chip, and three photodetectors (PDs) that receive data from the three different chips that belong to the other set. The output optical beam of a VCSEL element is coupled into an optical fiber connected to a 1x3 optical switch, implemented using an Opto-VLSI-based 4-f imaging system, as will be illustrated subsequently. The output fiber ports of the optical switches of a set are connected to the photodetectors associated with the chips of the other set, as illustrated in Fig. 2. The outputs of the photodetectors linked to a chip are connected to the receiving data port of that chip. In this way, the interconnection between two chips is mainly controlled by the Opto-VLSI switch. Figure 3
Fig. 3 Illustration of an array of 1x3 optical switches implemented using a single Opto-VLSI processor and a 4-f imaging system.
illustrates the Opto-VLSI processor and the 4-f imaging system used to implement the optical switches required for the reconfigurable optical interconnect architecture in Fig. 2. A lens, of focal length f, which collimates the divergent optical beam from the input optical fiber associated to a VCSEL element, is placed at a distance f from the fiber array. The vertical spacing between the input fiber and the optical axis of the lens is around a quarter of the fiber array spacing (250 µm). The collimated beam incident on the active window of the Opto-VLSI processor, which is placed at a distance f from the lens, can be steered to any of the three fiber ports, associated to the lens, using phase holograms (or blazed gratings) uploaded onto the Opto-VLSI processor, as illustrated in Fig. 1. Note that several 1x3 switches can be realized using a single Opto-VLSI processor partitioned into several pixel blocks that are independently driven by appropriate steering phase holograms.

4. 4-f imaging system operation

Figure 4
Fig. 4 Illustration of the principle of switching operations. (a) Without a hologram, the collimated optical beam reflects back and focuses on a spot between the two fibers; (b) With hologram H23 on, a +1st order diffracted beam is focused on and coupled into the fiber 3; (c) With hologram H21 on, a −1st order diffracted beam is focused on and coupled into the fiber 1, (d) With hologram H24 on, a +1st order diffracted beam is focused on and coupled into the fiber 4.
illustrates the principle of the 4-f imaging system used in the optical interconnect architecture. When a blank phase hologram drives a pixel block of the Opto-VLSI processor, the optical beam diverging from the input optical fiber (fiber 2) is collimated by the 4-f imaging lens, reflected back by the Opto-VLSI processor (0th-order diffraction), and then focused by the same lens onto a spot between the upper and lower optical fibers so that negligible optical power (or crosstalk) is coupled into both upper and lower fibers, as illustrated in Fig. 4(a). By driving the Opto-VLSI processor with optimized steering holograms, the input collimated beam carrying data can be steered and coupled to either optical fiber 3 or 4 ( +1st-order diffracted beams) or to optical fiber 1 (−1st-order diffracted beam) as illustrated in Figs. 4(b-d). According to Eq. (1), both +1st-order diffraction and −1st-order diffraction can have their steering angles changed by resetting the phase hologram (or blazed grating) parameters.

5. Experiments and results

5.1 Switching operation of optical signals

In order to demonstrate the principle of the proposed optical interconnect architecture shown in Fig. 2, an experiment was set up to measure the output optical intensities from different fiber port through a 1x3 Opto-VLSI switch, as illustrated in Fig. 5
Fig. 5 Experimental system for measuring the optical intensities at the three output ports of the optical interconnect system. Optical signal from a laser source is input through fiber 2 and the three fibers are used for output ports for receiving the steered beams by the Opto-VLSI processor. Two optical spectrum analyzers OSA1 and OSA2 are used to measure optical intensities for both signal and crosstalk.
. A 1-D 256-phase 4096-pixel Opto-VLSI processor was used. Each pixel has an area of 6mm×1µm with a dead space between adjacent pixels of 0.8µm. An off-the-shelf 16-port fiber array of fiber spacing 250µm was used and aligned to a lens of focal length 12.5mm. The Opto-VLSI processor was placed at 12.5mm from the lens and aligned to form a 4-f imaging system in conjunction with the lens. Three optimized phase holograms were synthesized to steer the input optical beam of λ=1550nm from a laser source into fiber ports 1, 3 and 4 via fiber 2, respectively. Two optical spectrum analyzers (OSAs) were used to monitor the output signal intensities and crosstalk levels, respectively. In this demonstration, sufficiently large holograms were generated and uploaded into the active area of the Opto-VLSI processor for dynamic optical beam steering.

Figure 6
Fig. 6 Measured optical spectra from fiber 3 and fiber 4 and the crosstalk intensities detected by the OSA1 and OSA2.
shows the measured optical spectra of the output signals from fiber 3 and fiber 4, which had the highest power level and lowest power level, respectively. The optical power level of fiber port 1 was between that of fiber 3 and fiber 4, as listed in Table 1

Table 1. The intensities of signals and crosstalk levels from the five fiber ports measured by OSA1 and OSA2 (Fig. 5).

table-icon
View This Table
. The input optical power launched to fiber 2 was +4.7dBm. Therefore, the optical switching losses were 5.8dBm for fiber 3 and 9.6dBm for fiber 4. This included fiber-to-fiber beam coupling loss, the Opto-VLSI processor loss, polarization dependent loss of around 0.6dB. The loss of fiber connectors in the system was 0.2dB. The non-uniform optical switching loss through the different output ports is mainly due to the fact that the diffraction efficiency of a steering hologram decreases with increasing the steering angle [24

24. J. Stockley, and S. Serati, “Advances in liquid crystal beam steering,” Boulder Nonlinear Systems, www.bnonliner.com, (2004).

]. The crosstalk, defined as the ratio of the measured optical signal power at the intended fiber port and the maximum crosstalk power detected at the other fiber ports, was less than −36.4dB for all of the three output signals.

5.2 Eye diagram measurements

Figure 7
Fig. 7 Experimental setup for measuring the eye diagram of the optical interconnect architecture. Opto-VLSI processor switches modulated optical signal from Fiber 2 to Fiber 4. Insertion loss due to optical switching is around 9.6 dB (worst-case scenario).
shows the experiment that was set up to investigate the eye diagrams for data transmission through the proposed reconfigurable optical interconnects. Data synthesized by a high-speed pattern generator was used to modulate a 1550nm laser light via an electro-optic intensity modulator. A polarization controller was used to maximize the modulated optical intensity. The modulated optical signal was launched into optical fiber port 2 and switched via the 4-f imaging system to port 4. This switching scenario corresponds to the worst-case insertion loss of the Opto-VLSI-based switching operation. The switched optical signal was detected by a high-speed photo-receiver and the photodetected data was monitored by a digitizing oscilloscope, where eye diagrams were displayed. Both the modulator and the photo-receiver used in the experiment have bandwidths exceeding 12GHz.

Figure 8
Fig. 8 Measured eye diagrams for transmitted data rate of 2Gb/s, 5Gb/s, 10Gb/s and 12Gb/s through the reconfigurable optical interconnect system.
shows the eye diagrams that were measured by the digitizing oscilloscope for the data rates 2Gb/s, 5Gb/s, 10Gb/s and 12Gb/s, respectively. It can be seen that the eye opening is large enough at 10Gb/s, however, it is reduced at 12Gb/s due to the reduction in signal-to-noise ratio of the transmitted data. The experiments shown in Fig. 5 and Fig. 7 and the results demonstrate the principle of the proposed reconfigurable optical interconnect architecture for high-speed chip-to-chip and board-to-board data communications.

6. Conclusion

We have presented and demonstrated experimentally a novel reconfigurable optical interconnect architecture for chip-to-chip and board-to-board high-speed data communications. The interconnect architecture employs a single Opto-VLSI processor to realize six 1x3 optical switches based on 4-f imaging. The capability of the Opto-VLSI processor to reconfigure optical interconnects has been demonstrated through the steering of modulated optical signals from an input optical fiber port to any output fiber ports by means of computer-generated holograms. Experimental results have shown that the optical switching losses range from 5.8dB to 9.6dB depending on the input-output fiber port combination, and that the crosstalk level is less than −36dB. Data transmission and eye diagram measurements have also been carried out at different bit rates, and demonstrated a large eye opening for bit rates below 10Gb/s. The proposed reconfigurable optical interconnect architecture has potential for applications in high performance computing and adaptive signal processing.

References and links

1.

R. Lytel, H. L. Davidson, N. Nettleton, and T. Sze, “Optical interconnections within modern high-performance computing systems,” Proc. IEEE 88(6), 758–763 ( 2000). [CrossRef]

2.

D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE 88(6), 728–749 ( 2000). [CrossRef]

3.

E. E. E. Frietman, R. J. Ernst, R. Crosbie, and M. Shimoji, “Prospects for optical interconnects in distributed shared-memory organized MIMD architectures,” J. Supercomput. 14(2), 107–128 ( 1999). [CrossRef]

4.

A. V. Krishnamoorthy, X. Zheng, J. E. Cunningham, J. Lexau, R. Ho, and O. Torudbakken, “Optical interconnects for present and future high-performance computing systems,” Proceedings of 16th IEEE Symposium on High Performance Interconnects, 175–177 (2008).

5.

D. A. B. Miller, “Physical reasons for optical interconnection,” (Special Issue on Smart Pixels) J. Optoelectron. 11, 155 ( 1997).

6.

J. A. Kash, “Leveraging optical interconnects in future supercomputers and servers,” Proceedings of the 16th IEEE Symposium on High Performance Interconnects, 190–194 (2008).

7.

T. D. Wilkinson, C. Henderson, D. Gilleyva, B. Robertson, D. O’Brien, and G. Faulkner, “Adaptive optical interconnect using an FLC SLM,” Ferroelectrics 312, 81–85 ( 2004). [CrossRef]

8.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic, “Building manycore processor-to-DRAM networks with monolithic silicon photonics,” Proceedings of 16th IEEE Symposium on High Performance Interconnects, 21–30 (2008).

9.

O. Liboiron-Ladouceur, H. Wang, A. S. Garg, and K. Bergman, “Low-power, transparent optical network interface for high bandwidth off-chip interconnects,” Opt. Express 17(8), 6550–6561 ( 2009). [CrossRef] [PubMed]

10.

A. K. Kodi and A. Louri, “Multidimensional and reconfigurable optical interconnects for high-performance computing (HPC) systems,” J. Lightwave Technol. 27(21), 4634–4641 ( 2009). [CrossRef]

11.

R. T. Chen, L. Lin, C. Choi, Y. J. Liu, B. Bihari, L. Wu, S. Tang, R. Wickman, B. Picor, M. K. Hibbsbrenner, J. Bristow, and Y. S. Liu, “Fully embedded board-level guided-wave optoelectronic interconnects,” Proc. IEEE 88(6), 780–793 ( 2000). [CrossRef]

12.

F. Mederer, R. Jager, H. J. Unold, R. Michalzik, K. J. Ebeling, S. Lehmacher, A. Neyer, and E. Griese, “3- Gb/s data transmission with GaAs VCSEL’s over PCB integrated polymer waveguides,” IEEE Photon. Technol. Lett. 13(9), 1032–1034 ( 2001). [CrossRef]

13.

B. E. Lemoff, M. E. Ali, G. Panotopoulos, G. M. Flower, B. Madhavan, A. F. J. Levi, and D. W. Dolfi, “MAUI: Enabling fiber-to-the-Processor with parallel multiwavelength optical interconnects,” J. Lightwave Technol. 22(9), 2043–2054 ( 2004). [CrossRef]

14.

L. A. Buckman Windover, J. N. Simon, S. A. Rosenau, K. Giboney, G. M. Flower, L. W. Mirkarimi, A. Grot, B. Law, C. K. Lin, A. Tandon, R. W. Gruhlke, H. Xia, G. Rankin, and D. W. Dolfi, “Parallel optical interconnects beyond > 100 Gb/s,” J. Lightwave Technol. 22(9), 2055–2063 ( 2004). [CrossRef]

15.

Y. Li, J. Ai, and J. Popelek, “Board-level 2-D data-capable optical interconnect circuits using polymer fiber-image guides,” Proc. IEEE 88(6), 794–805 ( 2000). [CrossRef]

16.

T. Maj, A. G. Kirk, D. V. Plant, J. F. Ahadian, C. G. Fonstad, K. L. Lear, K. Tatah, M. S. Robinson, and J. A. Trezza, “Interconnection of a two-dimensional array of vertical-cavity surface-emitting lasers to a receiver array by means of a fiber image guide,” Appl. Opt. 39(5), 683–689 ( 2000). [CrossRef] [PubMed]

17.

C. J. Henderson, D. G. Leyva, and T. D. Wilkinson, “Free space adaptive optical interconnect at 1.25 Gb/s with beam steering using a ferroelectric liquid-crystal SLM,” J. Lightwave Technol. 24(5), 1989–1997 ( 2006). [CrossRef]

18.

S. Agelis, and M. Jonsson, “Reconfigurable optical interconnection system supporting concurrent application-specific parallel computing,” Proceedings of the 17th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD’05), 2005.

19.

F. Wippermann, D. Radtke, M. Amberg, and S. Sinzinger, “Integrated free-space optical interconnect fabricated in planar optics using chirped microlens arrays,” Opt. Express 14(22), 10765–10778 ( 2006). [CrossRef] [PubMed]

20.

D. V. Plant and A. G. Kirk, “Optical interconnects at the chip and board level: Challenges and solutions,” Proc. IEEE 88(6), 806–818 ( 2000). [CrossRef]

21.

J. J. Liu, Z. Kalayjian, B. Riely, W. Chang, G. J. Simonis, A. Apsel, and A. Andreou, “Multichannel ultrathin silicon-on-sapphire optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9(2), 380–386 ( 2003). [CrossRef]

22.

N. McArdle, M. Naruse, H. Toyoda, Y. Kobayashi, and M. Ishikawa, “Reconfigurable optical interconnections for parallel computing,” Proc. IEEE 88(6), 829–837 ( 2000). [CrossRef]

23.

M. Aljada, K. E. Alameh, Y. T. Lee, and I. S. Chung, “High-speed (2.5 Gbps) reconfigurable inter-chip optical interconnects using opto-VLSI processors,” Opt. Express 14(15), 6823–6836 ( 2006). [CrossRef] [PubMed]

24.

J. Stockley, and S. Serati, “Advances in liquid crystal beam steering,” Boulder Nonlinear Systems, www.bnonliner.com, (2004).

25.

K. M. Johnson, D. J. McKnight, and I. Underwood, “Smart spatial light modulators using liquid crystals on silicon,” IEEE J. Quantum Electron. 29(2), 699–714 ( 1993). [CrossRef]

26.

J. W. Goodman and A. M. Silvestri, “Some effects of Fourier-domain phase quantization,” IBM J. Res. Develop. 14(9), 478–484 ( 1970). [CrossRef]

OCIS Codes
(060.6718) Fiber optics and optical communications : Switching, circuit

ToC Category:
Fiber Optics and Optical Communications

History
Original Manuscript: October 19, 2009
Revised Manuscript: November 18, 2009
Manuscript Accepted: November 19, 2009
Published: November 25, 2009

Citation
Mingya Shen, Feng Xiao, and Kamal Alameh, "A novel reconfigurable optical interconnect architecture using an Opto-VLSI processor and a 4-f imaging system," Opt. Express 17, 22680-22688 (2009)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-17-25-22680


Sort:  Author  |  Year  |  Journal  |  Reset  

References

  1. R. Lytel, H. L. Davidson, N. Nettleton, and T. Sze, “Optical interconnections within modern high-performance computing systems,” Proc. IEEE 88(6), 758–763 (2000). [CrossRef]
  2. D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE 88(6), 728–749 (2000). [CrossRef]
  3. E. E. E. Frietman, R. J. Ernst, R. Crosbie, and M. Shimoji, “Prospects for optical interconnects in distributed shared-memory organized MIMD architectures,” J. Supercomput. 14(2), 107–128 (1999). [CrossRef]
  4. A. V. Krishnamoorthy, X. Zheng, J. E. Cunningham, J. Lexau, R. Ho, and O. Torudbakken, “Optical interconnects for present and future high-performance computing systems,” Proceedings of 16th IEEE Symposium on High Performance Interconnects, 175–177 (2008).
  5. D. A. B. Miller, “Physical reasons for optical interconnection,” (Special Issue on Smart Pixels) J. Optoelectron. 11, 155 (1997).
  6. J. A. Kash, “Leveraging optical interconnects in future supercomputers and servers,” Proceedings of the 16th IEEE Symposium on High Performance Interconnects, 190–194 (2008).
  7. T. D. Wilkinson, C. Henderson, D. Gilleyva, B. Robertson, D. O’Brien, and G. Faulkner, “Adaptive optical interconnect using an FLC SLM,” Ferroelectrics 312, 81–85 (2004). [CrossRef]
  8. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic, “Building manycore processor-to-DRAM networks with monolithic silicon photonics,” Proceedings of 16th IEEE Symposium on High Performance Interconnects, 21–30 (2008).
  9. O. Liboiron-Ladouceur, H. Wang, A. S. Garg, and K. Bergman, “Low-power, transparent optical network interface for high bandwidth off-chip interconnects,” Opt. Express 17(8), 6550–6561 (2009). [CrossRef] [PubMed]
  10. A. K. Kodi and A. Louri, “Multidimensional and reconfigurable optical interconnects for high-performance computing (HPC) systems,” J. Lightwave Technol. 27(21), 4634–4641 (2009). [CrossRef]
  11. R. T. Chen, L. Lin, C. Choi, Y. J. Liu, B. Bihari, L. Wu, S. Tang, R. Wickman, B. Picor, M. K. Hibbsbrenner, J. Bristow, and Y. S. Liu, “Fully embedded board-level guided-wave optoelectronic interconnects,” Proc. IEEE 88(6), 780–793 (2000). [CrossRef]
  12. F. Mederer, R. Jager, H. J. Unold, R. Michalzik, K. J. Ebeling, S. Lehmacher, A. Neyer, and E. Griese, “3- Gb/s data transmission with GaAs VCSEL’s over PCB integrated polymer waveguides,” IEEE Photon. Technol. Lett. 13(9), 1032–1034 (2001). [CrossRef]
  13. B. E. Lemoff, M. E. Ali, G. Panotopoulos, G. M. Flower, B. Madhavan, A. F. J. Levi, and D. W. Dolfi, “MAUI: Enabling fiber-to-the-Processor with parallel multiwavelength optical interconnects,” J. Lightwave Technol. 22(9), 2043–2054 (2004). [CrossRef]
  14. L. A. Buckman Windover, J. N. Simon, S. A. Rosenau, K. Giboney, G. M. Flower, L. W. Mirkarimi, A. Grot, B. Law, C. K. Lin, A. Tandon, R. W. Gruhlke, H. Xia, G. Rankin, and D. W. Dolfi, “Parallel optical interconnects beyond > 100 Gb/s,” J. Lightwave Technol. 22(9), 2055–2063 (2004). [CrossRef]
  15. Y. Li, J. Ai, and J. Popelek, “Board-level 2-D data-capable optical interconnect circuits using polymer fiber-image guides,” Proc. IEEE 88(6), 794–805 (2000). [CrossRef]
  16. T. Maj, A. G. Kirk, D. V. Plant, J. F. Ahadian, C. G. Fonstad, K. L. Lear, K. Tatah, M. S. Robinson, and J. A. Trezza, “Interconnection of a two-dimensional array of vertical-cavity surface-emitting lasers to a receiver array by means of a fiber image guide,” Appl. Opt. 39(5), 683–689 (2000). [CrossRef] [PubMed]
  17. C. J. Henderson, D. G. Leyva, and T. D. Wilkinson, “Free space adaptive optical interconnect at 1.25 Gb/s with beam steering using a ferroelectric liquid-crystal SLM,” J. Lightwave Technol. 24(5), 1989–1997 (2006). [CrossRef]
  18. S. Agelis, and M. Jonsson, “Reconfigurable optical interconnection system supporting concurrent application-specific parallel computing,” Proceedings of the 17th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD’05), 2005.
  19. F. Wippermann, D. Radtke, M. Amberg, and S. Sinzinger, “Integrated free-space optical interconnect fabricated in planar optics using chirped microlens arrays,” Opt. Express 14(22), 10765–10778 (2006). [CrossRef] [PubMed]
  20. D. V. Plant and A. G. Kirk, “Optical interconnects at the chip and board level: Challenges and solutions,” Proc. IEEE 88(6), 806–818 (2000). [CrossRef]
  21. J. J. Liu, Z. Kalayjian, B. Riely, W. Chang, G. J. Simonis, A. Apsel, and A. Andreou, “Multichannel ultrathin silicon-on-sapphire optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9(2), 380–386 (2003). [CrossRef]
  22. N. McArdle, M. Naruse, H. Toyoda, Y. Kobayashi, and M. Ishikawa, “Reconfigurable optical interconnections for parallel computing,” Proc. IEEE 88(6), 829–837 (2000). [CrossRef]
  23. M. Aljada, K. E. Alameh, Y. T. Lee, and I. S. Chung, “High-speed (2.5 Gbps) reconfigurable inter-chip optical interconnects using opto-VLSI processors,” Opt. Express 14(15), 6823–6836 (2006). [CrossRef] [PubMed]
  24. J. Stockley, and S. Serati, “Advances in liquid crystal beam steering,” Boulder Nonlinear Systems, www.bnonliner.com, (2004).
  25. K. M. Johnson, D. J. McKnight, and I. Underwood, “Smart spatial light modulators using liquid crystals on silicon,” IEEE J. Quantum Electron. 29(2), 699–714 (1993). [CrossRef]
  26. J. W. Goodman and A. M. Silvestri, “Some effects of Fourier-domain phase quantization,” IBM J. Res. Develop. 14(9), 478–484 (1970). [CrossRef]

Cited By

Alert me when this paper is cited

OSA is able to provide readers links to articles that cite this paper by participating in CrossRef's Cited-By Linking service. CrossRef includes content from more than 3000 publishers and societies. In addition to listing OSA journal articles that cite this paper, citing articles from other participating publishers will also be listed.


« Previous Article  |  Next Article »

OSA is a member of CrossRef.

CrossCheck Deposited