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Optics Express

  • Vol. 17, Iss. 7 — Mar. 30, 2009
  • pp: 5118–5124
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Deposited silicon high-speed integrated electro-optic modulator

Kyle Preston, Sasikanth Manipatruni, Alexander Gondarenko, Carl B. Poitras, and Michal Lipson  »View Author Affiliations


Optics Express, Vol. 17, Issue 7, pp. 5118-5124 (2009)
http://dx.doi.org/10.1364/OE.17.005118


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Abstract

We demonstrate a micrometer-scale electro-optic modulator operating at 2.5 Gbps and 10 dB extinction ratio that is fabricated entirely from deposited silicon. The polycrystalline silicon material exhibits properties that simultaneously enable high quality factor optical resonators and sub-nanosecond electrical carrier injection. We use an embedded p+n-n+ diode to achieve optical modulation using the free carrier plasma dispersion effect. Active optical devices in a deposited microelectronic material can break the dependence on the traditional single layer silicon-on-insulator platform and help lead to monolithic large-scale integration of photonic networks on a microprocessor chip.

© 2009 Optical Society of America

1. Introduction

Fig. 1. Polysilicon electro-optic modulator device structure. (a) Top view schematic showing the doping regions of the device that form a p+-n--n+ diode around a ring resonator. (b) Tilted view colorized scanning electron microscope (SEM) image. The polysilicon resonator and 450 nm-wide bus waveguide are buried under 1 μm silicon dioxide. (c) Cross-section schematic of the device (not to scale).

2. Polysilicon material properties and device fabrication

The polysilicon material system differs from single-crystalline silicon in three critical ways that affect electro-optic modulator design and performance: effective carrier mobility (μeff), effective free carrier lifetime (τfc), and optical loss. All three parameters are affected by the grain boundaries that exist throughout the material. For instance, grain boundaries in polysilicon present a potential barrier to the flow of carriers which results in decreased effective carrier mobility μeff [21

21. T. Kamins, Polycrystalline Silicon for Integrated Circuits and Displays, 2nd ed. (Kluwer, 1998). [CrossRef]

, 30

30. C. R. M. Grovenor, “Grain boundaries in semiconductors,” J. Phys. C 18, 4079–4119 (1985). [CrossRef]

]. Mobility in various phases of silicon ranges from the order of 1,000 cm2/V·s (single crystalline silicon) to less than 1 cm2/V·s (amorphous silicon).

Background doping of the device region is required to ensure sufficient charge injection because intrinsic undoped polysilicon is extremely resistive (corresponding to low mobility μ) [21

21. T. Kamins, Polycrystalline Silicon for Integrated Circuits and Displays, 2nd ed. (Kluwer, 1998). [CrossRef]

]. An increase in doping above the grain boundary trap density improves the electrical injection [21

21. T. Kamins, Polycrystalline Silicon for Integrated Circuits and Displays, 2nd ed. (Kluwer, 1998). [CrossRef]

, 28

28. S. V. Karnik and M. K. Hatalis, “Lateral polysilicon p+-p-n+ and p+-n-n+ diodes,” Solid-State Electron. 47, 653–659 (2003). [CrossRef]

], but this is a tradeoff with increased optical loss due to free carrier absorption [29

29. R. Soref and B. Bennett, “Electrooptical effects in silicon,” IEEE J. Quantum Electron. 23, 123–129 (1987). [CrossRef]

]. In doped polysilicon, some percent of dopant atoms segregate to low energy positions at the grain boundaries where they do not contribute carriers. Additionally, the carriers themselves can fill in grain boundary trap states [21

21. T. Kamins, Polycrystalline Silicon for Integrated Circuits and Displays, 2nd ed. (Kluwer, 1998). [CrossRef]

] where they will not contribute to free carrier dispersion. To keep the background free carrier losses low, we conservatively choose an average n-type doping level Nd ≈ 2·1017 cm-3. We estimate that this produces a free carrier concentration n ≤ 1017 cm-3 which keeps excess free carrier loss below 4 dB/cm [29

29. R. Soref and B. Bennett, “Electrooptical effects in silicon,” IEEE J. Quantum Electron. 23, 123–129 (1987). [CrossRef]

].

Fabrication of the devices is performed using standard microelectronic processes. We start with a silicon wafer and grow a 3 μm thermal oxide isolation layer. We then deposit a 270 nm layer of amorphous silicon by low pressure chemical vapor deposition (LPCVD) at 550°C and crystallize the film into polysilicon by a thermal anneal at a maximum temperature of 1100°C. Background doping of the resonator area is done by opening windows in positive e-beam resist and performing Phosphorus ion implantation with a dose of 4.7×1012 cm-2 and energy of 130 keV. We pattern waveguides and resonators using e-beam lithography and XR-1541 resist, and transfer the pattern using chlorine-based inductively coupled plasma reactive ion etching (ICP-RIE), leaving a 40 nm slab of silicon for electrical access. We dope p+ and n+ contact regions in the slab by BF2 and Phosphorus ion implantation at 1.2×1015 cm-2 dose and clad the structures in 1 μm silicon dioxide by plasma enhanced chemical vapor deposition (PECVD). We then anneal the sample in N2 for 30 minutes at 600°C, 15 minutes at 900°C, and 15 seconds at 1050°C for silicon regrowth and dopant activation. (By ending with the high temperature rapid thermal anneal, we maximize the number of dopant ions that are electrically active [21

21. T. Kamins, Polycrystalline Silicon for Integrated Circuits and Displays, 2nd ed. (Kluwer, 1998). [CrossRef]

].) Finally we open vias to the contact regions in order to form nickel silicide contacts and aluminum pads using e-beam evaporation and liftoff steps. The device consists of a 10 μm radius polysilicon ring resonator embedded in a 40 nm tall p+-n--n+ diode and laterally coupled to a polysilicon waveguide. A cross-sectional schematic, top view schematic, and top view microscope image are shown in Figure 1.

3. Results

We first analyze the electro-optic device with DC measurements. Optical measurements are performed using a tunable infrared laser coupled through a polarization controller to a tapered lens fiber. Light is coupled on and off chip via nanotaper mode converters. Output from the chip is collected by an objective lens, passed through a polarization filter, and focused on a photodetector. Figure 2(a) shows a measured resonance at λ0 = 1550.35 nm with spectral 3 dB width ∆λFWHM = 0.45 nm, quality factor Q = λ0/∆λFWHM = 3,400 and 16 dB extinction ratio. Other devices from this fabrication run exhibited quality factors exceeding 10,000. We perform a DC electrical measurement on the device to obtain a diode IV curve shown in Fig. 2(b). The device exhibits an on-resistance of approximately 3.5 kΩ, which includes contact resistance at the p+ and n+ regions and series resistance through the lightly doped waveguide and slab regions.

Fig. 2. DC optical and electrical measurements. (a) Wavelength scan showing through port transmission for quasi-TM polarization with quality factor Q = λ0/∆λFWHM = 3,400 and 16 dB extinction ratio. (b) Electrical IV curve demonstrating DC diode characteristics.

We demonstrate 2.5 Gbps modulation and measure a 10 dB modulation depth with a NRZ 27-1 PRBS electrical signal applied with a ±4V swing and a 4V DC bias. For AC measurements, output light from the chip is collimated, coupled to a fiber, passed through a fiber pre-amplifier and tunable filter, and recorded by an oscilloscope with a 20 GHz photodetector. The oscilloscope is triggered to the pattern generator which provides the NRZ electrical signal to a high-speed amplifier and bias T circuit. By forward biasing the diode and injecting free carriers into the ring, the resonant wavelength blue shifts and changes the probe wavelength transmission from low to high. Figure 3(a) and (b) show the optical transmission and frame-averaged optical eye diagram when the wavelength is tuned to minimize the off-state transmission. The slight overshoot and oscillation of the high transmission of the waveform in Fig. 3 is caused by electrical impedance mismatch, coupled with the fact that the voltage swing here is not sufficient to reach full optical transmission. Comparing the measured 10 dB extinction ratio in Fig. 3(a) to the 16 dB extinction on resonance in Fig. 2(a), we estimate a 6 dB insertion loss and a maximum wavelength shift ∆λ ≈ 130 pm. This ∆λ corresponds to an effective index shift ∆neff = ngλ/λ0 = 3.66×10-4 given a group index ng = 4.36 found with a finite difference modesolver program. Based on modesolver simulation, this ∆neff is caused by a silicon refractive index change ∆n =3.7×10-4, which is caused by a carrier injection level ∆N = ∆P = 8.4×1016 cm-3 [29

29. R. Soref and B. Bennett, “Electrooptical effects in silicon,” IEEE J. Quantum Electron. 23, 123–129 (1987). [CrossRef]

]. We estimate energy consumption of 950 fJ/bit and power consumption of 2.4 mW based on the voltage swing, bit rate, carrier lifetime, device size, and charge injection levels.

The carrier mobility μ can be estimated from the measured DC on-resistance using the formula [28

28. S. V. Karnik and M. K. Hatalis, “Lateral polysilicon p+-p-n+ and p+-n-n+ diodes,” Solid-State Electron. 47, 653–659 (2003). [CrossRef]

]:

Ron=1qμnw(Lslabhslab+Lwghwg)
(1)

where q is the electron charge, n is the free carrier concentration (~1017 cm-3), w is the circumference of the ring (62.8 μm), Lslab is the total cross-section length of the slab region between the n+ and p+ regions (1.55 μm), Lwg is the width of the waveguide (0.45 μm), hslab is the height of the polysilicon slab (40 nm), and hwg is the waveguide height (270 nm). By attributing the full 3.5 kΩ to material resistance, we calculate a first-order lower bound for the carrier mobility μ = 100 cm2/V·s. This is only one order of magnitude lower than values in crystalline silicon [21

21. T. Kamins, Polycrystalline Silicon for Integrated Circuits and Displays, 2nd ed. (Kluwer, 1998). [CrossRef]

], which explains why the electrical performance can approach that seen in crystalline SOI devices.

We model the operation of the device using Silvaco Atlas simulation software and show excellent agreement with experimental results. As a first order model of the effect of grain boundaries on the polysilicon electrical properties, we define silicon bulk material properties within our device, including a free carrier lifetime τfc = 80 ps and an effective carrier mobility μn = 100 cm2/V·s for electrons and μp = 50 cm2/V·s for holes. We use Shockley-Read-Hall and Klaassen models for carrier recombination and mobility, and the surface recombination velocity is taken to be 16,000 cm/s which is consistent with SOI modeling [31

31. S. Manipatruni, Q. Xu, and M. Lipson, “PINIP based high-speed high-extinction ratio micron-size silicon electrooptic modulator,” Opt. Express 15, 13035–13042 (2007). [CrossRef] [PubMed]

]. We apply the same voltage signal as was used in Fig. 3(a) (without ringing) and solve for the transient charge concentrations ∆N(t) and ∆P(t) in the waveguide region. These values are then converted to a wavelength shift ∆λ(t) and excess loss ∆α(t) which are put into a Lorentzian resonance model to find the optical response. Note that a time domain optical model is not required because the cavity photon lifetime τp = /(2πc) = 2.7 ps is much less than the charge injection time. The result for optical transmission is shown in Fig. 3(c), which demonstrates excellent agreement in rise time, fall time, and extinction ratio with the experimental results in Fig. 3(a).

Fig. 3. Electro-optic response of the polysilicon modulator. (a) Optical transmission and (b) frame-averaged optical eye diagram for NRZ 2.5 Gbps 27-1 PRBS signal. (c) Simulation of electro-optic response using bulk distributed material parameters τfc = 80 ps, μn = 100 cm2/Vs, and μp = 50 cm2/Vs.

4. Discussion

The polysilicon device shown here demonstrates speed and energy consumption (2.5 Gbps and 950 fJ/bit) approaching those in state-of-the-art crystalline silicon microresonator devices (~ 20 Gbps and ~ 100 fJ/bit [9

9. S. Manipatruni, X. Qianfan, B. Schmidt, J. Shakya, and M. Lipson, “High Speed Carrier Injection 18 Gb/s Silicon Micro-ring Electro-optic Modulator,” in Proceedings of Lasers and Electro-Optics Society (IEEE, 2007), pp.537–538.

, 10

10. M. R. Watts, D. C. Trotter, R. W. Young, and A. L. Lentine, “Ultralow power silicon microdisk modulators and switches,” in 5th IEEE International Conference on Group IV Photonics (IEEE, 2008), pp. 4–6. [CrossRef]

]). The reduced carrier mobility μ in polysilicon necessitates the use of a slightly higher forward bias voltage for the on-state which increases power consumption, however this is partially compensated by the fast carrier recombination [26

26. K. Preston, P. Dong, B. Schmidt, and M. Lipson, “High-speed all-optical modulation using polycrystalline silicon microring resonators,” Appl. Phys. Lett. 92, 151104 (2008). [CrossRef]

] which eliminates the need for a reverse bias voltage for the off-state. The optical transmission in Fig. 3 exhibits a 90%–10% fall time of 120 ps with 0V applied for the off-state. The 10%-to-90% rise time in Fig. 3 is 150 ps, indicating a possible bit rate > 5 Gbps. With moderately improved Q and electrical characteristics, we expect the insertion loss could be reduced to near 0 dB and the speed increased to tens of Gbps using pre-emphasis techniques [32

32. Q. Xu, S. Manipatruni, B. Schmidt, J. Shakya, and M. Lipson, “12.5 Gbit/s carrier-injection-based silicon micro-ring silicon modulators,” Opt. Express 15, 430–436 (2007). [CrossRef] [PubMed]

].

Electrical properties of the device can be improved by two main approaches: optimizing the background doping concentration and decreasing the device size. The background doping strongly influences the electrical mobility and resistance obtained in the film, which in turn strongly affect the speed and power consumption [21

21. T. Kamins, Polycrystalline Silicon for Integrated Circuits and Displays, 2nd ed. (Kluwer, 1998). [CrossRef]

, 30

30. C. R. M. Grovenor, “Grain boundaries in semiconductors,” J. Phys. C 18, 4079–4119 (1985). [CrossRef]

]. Optimal conditions may be found at a higher doping concentration Nd that further improves the mobility without negatively affecting off-state Q. Energy consumption can be greatly reduced to potentially tens of fJ/bit by decreasing the size of the resonator to smaller microring [33

33. Q. Xu, D. Fattal, and R. G. Beausoleil, “Silicon microring resonators with 1.5-μm radius,” Opt. Express 16, 4309–4315 (2008). [CrossRef] [PubMed]

] or 1-D cavity geometries [34

34. J. S. Foresi, P. R. Villeneuve, J. Ferrera, E. R. Thoen, G. Steinmeyer, S. Fan, J. D. Joannopoulos, L. C. Kimerling, H. I. Smith, and E. P. Ippen, “Photonic-bandgap microcavities in optical waveguides,” Nature 390, 143–145 (1997). [CrossRef]

, 35

35. B. Schmidt, Q. Xu, J. Shakya, S. Manipatruni, and M. Lipson, “Compact electro-optic modulator on silicon-on-insulator substrates using cavities with ultra-small modal volumes,” Opt. Express 15, 3140–3148 (2007). [CrossRef] [PubMed]

], since switching energy scales inversely with resonator size [33

33. Q. Xu, D. Fattal, and R. G. Beausoleil, “Silicon microring resonators with 1.5-μm radius,” Opt. Express 16, 4309–4315 (2008). [CrossRef] [PubMed]

].

The primary consideration for photonic integration with the CMOS process flow is the temperature required for device fabrication [17

17. M. Beals, J. Michel, J. F. Liu, D. H. Ahn, D. Sparacin, R. Sun, C. Y. Hong, L. C. Kimerling, A. Pomerene, D. Carothers, J. Beattie, A. Kopa, A. Apsel, M. S. Rasras, D. M. Gill, S. S. Patel, K. Y. Tu, Y. K. Chen, and A. E. White, “Process flow innovations for photonic device integration in CMOS,” Proc. SPIE 6898, 689804 (2008). [CrossRef]

]. The highest temperature in our process is the 1100°C crystallization anneal which is used to maximize the grain size and minimize the optical loss [22

22. L. Liao, D. R. Lim, A. M. Agarwal, X. Duan, K. K. Lee, and L. C. Kimerling, “Optical transmission losses in polycrystalline silicon strip waveguides,” J. Electron. Mater. 29, 1380–1386 (2000). [CrossRef]

]. Because of the relatively high temperature, these devices would need to be fabricated before any doping or silicidation is performed on the silicon transistor layer. Note however that a high temperature thermal anneal is not fundamentally required for large grain polycrystalline films. Crystallization by nanosecond excimer laser annealing can be used to achieve grain sizes of micrometers without any steady state heating of the substrate. This technique is currently used extensively in the thin film transistor industry to produce polycrystalline films on glass and plastic substrates [36

36. A. T. Voutsas, “Laser Crystallization of Thin Films for Flat Panel Display Applications,” in Recent Advances in Laser Processing of Materials, J. Perriere, E. Millon, and E. Fogarassy, eds. (Elsevier, New York, 2006), pp. 317–373. [CrossRef]

]. With a low-temperature process below 450°C, active polysilicon devices could be integrated with low loss amorphous silicon or silicon nitride waveguides on top of the CMOS metal interconnect layers. This type of post-backend processing would enable optical functionality on a CMOS chip with minimal changes to the microelectronic process flow.

5. Conclusion

For the first time to our knowledge, we have demonstrated GHz-speed electro-optic modulation in a deposited microelectronic material. The polycrystalline silicon exhibits optical and electrical properties which enable modulation of the transmission through a microring resonator on a 150 ps timescale. This work represents a step towards adapting high-performance silicon photonic devices for monolithic large-scale integration with standard CMOS microelectronics.

Acknowledgments

This work was supported by Intel Corporation and supervised by M. Reshotko. The authors gratefully acknowledge C. Manolatou for the use of her finite difference code. This work was performed in part at the Cornell NanoScale Facility, a member of the National Nanotechnology Infrastructure Network, which is supported by the National Science Foundation (Grant ECS-0335765).

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11.

J.-B. You, M. Park, J.-W. Park, and G. Kim, “12.5 Gbps optical modulation of silicon racetrack resonator based on carrier-depletion in asymmetric p-n diode,” Opt. Express 16, 18340–18344 (2008). [CrossRef] [PubMed]

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22.

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26.

K. Preston, P. Dong, B. Schmidt, and M. Lipson, “High-speed all-optical modulation using polycrystalline silicon microring resonators,” Appl. Phys. Lett. 92, 151104 (2008). [CrossRef]

27.

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28.

S. V. Karnik and M. K. Hatalis, “Lateral polysilicon p+-p-n+ and p+-n-n+ diodes,” Solid-State Electron. 47, 653–659 (2003). [CrossRef]

29.

R. Soref and B. Bennett, “Electrooptical effects in silicon,” IEEE J. Quantum Electron. 23, 123–129 (1987). [CrossRef]

30.

C. R. M. Grovenor, “Grain boundaries in semiconductors,” J. Phys. C 18, 4079–4119 (1985). [CrossRef]

31.

S. Manipatruni, Q. Xu, and M. Lipson, “PINIP based high-speed high-extinction ratio micron-size silicon electrooptic modulator,” Opt. Express 15, 13035–13042 (2007). [CrossRef] [PubMed]

32.

Q. Xu, S. Manipatruni, B. Schmidt, J. Shakya, and M. Lipson, “12.5 Gbit/s carrier-injection-based silicon micro-ring silicon modulators,” Opt. Express 15, 430–436 (2007). [CrossRef] [PubMed]

33.

Q. Xu, D. Fattal, and R. G. Beausoleil, “Silicon microring resonators with 1.5-μm radius,” Opt. Express 16, 4309–4315 (2008). [CrossRef] [PubMed]

34.

J. S. Foresi, P. R. Villeneuve, J. Ferrera, E. R. Thoen, G. Steinmeyer, S. Fan, J. D. Joannopoulos, L. C. Kimerling, H. I. Smith, and E. P. Ippen, “Photonic-bandgap microcavities in optical waveguides,” Nature 390, 143–145 (1997). [CrossRef]

35.

B. Schmidt, Q. Xu, J. Shakya, S. Manipatruni, and M. Lipson, “Compact electro-optic modulator on silicon-on-insulator substrates using cavities with ultra-small modal volumes,” Opt. Express 15, 3140–3148 (2007). [CrossRef] [PubMed]

36.

A. T. Voutsas, “Laser Crystallization of Thin Films for Flat Panel Display Applications,” in Recent Advances in Laser Processing of Materials, J. Perriere, E. Millon, and E. Fogarassy, eds. (Elsevier, New York, 2006), pp. 317–373. [CrossRef]

OCIS Codes
(130.3120) Integrated optics : Integrated optics devices
(130.3130) Integrated optics : Integrated optics materials
(230.2090) Optical devices : Electro-optical devices

ToC Category:
Integrated Optics

History
Original Manuscript: February 9, 2009
Revised Manuscript: March 9, 2009
Manuscript Accepted: March 13, 2009
Published: March 17, 2009

Citation
Kyle Preston, Sasikanth Manipatruni, Alexander Gondarenko, Carl B. Poitras, and Michal Lipson, "Deposited silicon high-speed integrated electro-optic modulator," Opt. Express 17, 5118-5124 (2009)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-17-7-5118


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References

  1. D. A. B. Miller, "Rationale and challenges for optical interconnects to electronic chips," Proc. IEEE 88, 728-749 (2000). [CrossRef]
  2. A. Shacham, K. Bergman, and L. P. Carloni, "Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors," IEEE Trans. Comput. 57, 1246-1260 (2008). [CrossRef]
  3. A. Liu, R. Jones, L. Liao, D. Samara-Rubio, D. Rubin, O. Cohen, R. Nicolaescu, and M. Paniccia, "A high-speed silicon optical modulator based on a metal-oxide-semiconductor capacitor," Nature 427, 615-618 (2004). [CrossRef] [PubMed]
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