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Optics Express

Optics Express

  • Editor: C. Martijn de Sterke
  • Vol. 18, Iss. 18 — Aug. 30, 2010
  • pp: 19055–19063
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Highly-efficient thermally-tuned resonant optical filters

John E. Cunningham, Ivan Shubin, Xuezhe Zheng, Thierry Pinguet, Attila Mekis, Ying Luo, Hiren Thacker, Guoliang Li, Jin Yao, Kannan Raj, and Ashok V. Krishnamoorthy  »View Author Affiliations


Optics Express, Vol. 18, Issue 18, pp. 19055-19063 (2010)
http://dx.doi.org/10.1364/OE.18.019055


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Abstract

We demonstrate spectral tunability for microphotonic add-drop filters manufactured as ring resonators in a commercial 130 nm SOI CMOS technology. The filters are provisioned with integrated heaters built in CMOS for thermal tuning. Their thermal impedance has been dramatically increased by the selective removal of the SOI handler substrate under the device footprint using a bulk silicon micromachining process. An overall ~20x increase in the tuning efficiency has been demonstrated with a 100 µm radius ring as compared to a pre-micromachined device. A total of 3.9 mW of applied tuning power shifts the filter resonant peak across one free spectral node of the device. The Q-factor of the resonator remains unchanged after the co-integration process and hence this device geometry proves to be fully CMOS compatible. Additionally, after the cointegration process our result of 2π shift with 3.9mW power is among the best tuning performances for this class of devices. Finally, we examine scaling the tuning efficiency versus device footprint to develop a different performance criterion for an easier comparison to evaluate thermal tuning. Our criterion is defined as the unit of power to shift the device resonance by a full 2π phase shift.

© 2010 OSA

1. Introduction

A number of prior efforts [7

7. I. Christiaens, D. Van Thourhout, and R. Baets, “Low-power thermo-optic tuning of vertically coupled microring resonators,” Electron. Lett. 40(9), 560–561 (2004). [CrossRef]

12

12. I. Shubin, “X. Zheng, H. Thacker, J. Yao, J. Costa, Y. Luo, G. Li, A. V. Krishnamoorthy, J.E. Cunningham, T. Pinguet, A. Mekis, “Thermally tunable SOI CMOS photonics circuits,” Proc. SPIE 7607, 76070C (2010). [CrossRef]

] have addressed tuning of the microphotonic devices and micro-resonators under thermal control. One of the key metrics quantifying tuning quality has been the so called “tuning efficiency”. Typical values are about 4 mW/nm [7

7. I. Christiaens, D. Van Thourhout, and R. Baets, “Low-power thermo-optic tuning of vertically coupled microring resonators,” Electron. Lett. 40(9), 560–561 (2004). [CrossRef]

] that were measured for III-V rings while silicon photonic rings built on the SOI substrate report a similar thermal tuning efficiency [8

8. F. Gan, T. Barwicz, M. A. Popović, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kärtner, “Maximizing the Thermo-Optic Tuning Range of Silicon Photonic Structures,” IEEE Photon. Switching 67–68 (2007). [CrossRef]

]. In other efforts the tuning efficiency has been improved by 5x when combining shrinking the device footprint and direct filter heating [11

11. M. R. Watts, W. A. Zortman, D. C. Trotter, G. N. Nielson, D. L. Luck, and R. W. Young, “Adiabatic resonant microrings (ARMs) with directly integrated thermal microphotonics”, 2009 Conference on Lasers and Electro-Optics CLEO/QELS, CPDB10 (2009).

]. Still, it has been particularly challenging to quantify the metric of thermal efficiency reported in the literature and extract relative performance in a meaningful way when comparing resonant devices of different structure and layout.

In CMOS based resonators the heat generated in the ring is dissipated through heat spreading in the substrate and in the top metal, dielectric stack up. Because the thermal conductivity of the crystalline substrate underneath the ring is so large then significant power must be applied to shift the resonance across its free spectral range to align to a laser channel and correct potential mismatches of a 2π phase shift or more. The main purpose of our communication is to report a 20x improvement in tuning efficiency of a ring MUX filter upon co-integration of a back-side etch pit with silicon micromachining technology. The selective removal of the entire SOI handler substrate under the device footprint has substantially increased the device thermal impedance and dramatically improved tuning performance. A second objective of this communication is to clarify some of the other issues affecting the so called “tuning efficiency” metric by examining how tuning performance scales as the device footprint shrinks. Based on this perspective of scaling we introduce a new figure of merit that is defined as the power to shift a full 2π range in the device resonance. The benefit of this new metric is to develop a more effective figure of merit to quantify the actual efficiency for thermal tuning of this class of devices for WDM applications.

2. Device description

Thermal tuning of our resonators was accomplished with structures designed and implemented in a commercial, high yield, 130nm SOI CMOS process. More specifically the devices were built on Freescales’ 130 nm process node that consists of six metal layers of Cu intertwined with interlayer dielectrics composed principally of silicon nitride (SiNx) and silicon dioxide (SiO2). We can expect the structural integrity of the Cu, silicon nitrides and dioxides to have characteristics inherent to PVD, CVD and PECVD grown layers respectively, since they are a generic property common to nearly all CMOS technologies. Furthermore, the thermal and electrical transport characteristics of these films may differ substantially from bulk properties. Rings of different diameters (24 µm, 40 µm, 60 µm and 200 μm) were fabricated and characterized. Their cross-section is schematically illustrated in Fig. 1a
Fig. 1 Thermally tunable resonant waveguide structures: (a) schematic cross-section, (b) SEM image of the silicon waveguide ring with 24 µm diameter and its bus waveguides without the metal interconnects and interlayer dielectrics.
. A typical reported tunable circuit configuration positions the metal heater above the optical silicon waveguide with a dielectric layer in between [7

7. I. Christiaens, D. Van Thourhout, and R. Baets, “Low-power thermo-optic tuning of vertically coupled microring resonators,” Electron. Lett. 40(9), 560–561 (2004). [CrossRef]

,8

8. F. Gan, T. Barwicz, M. A. Popović, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kärtner, “Maximizing the Thermo-Optic Tuning Range of Silicon Photonic Structures,” IEEE Photon. Switching 67–68 (2007). [CrossRef]

]. In this approach the temperature of the optical waveguide is raised in its vicinity with an appreciable fraction of tuning power potentially radiated away from it.

In our rings the electrical current is forced directly through the optical ring waveguide by lateral conduction. Multiple tungsten plugs connect to the doped silicon slab that carries the waveguide. Therefore the temperature is raised in the optical signal path potentially improving the tuning power efficiency. Figure 1b contains SEM image of the waveguide ring with two straight waveguide buses and the thermally active silicon slab sections. The slab is formed around the waveguides by a complete silicon removal down to the underlying buried silicon oxide therefore further isolating the areas elevated in temperature and increasing the structure’s thermal impedance. The 24 µm diameter ring filter is shown without the dielectric CMOS layers and its metal interconnects to better visualize its details. Figure 2
Fig. 2 A fragment of the MUX/DEMUX circuit with two thermally tunable rings and their respective waveguide ports.
is a top view optical micrograph of the manufactured tunable filter circuit with a respective scale. The indicated optical ports are based on the grating couplers and are immediately accessed by the external optical fibers.

Our ring MUXes are based on ridge waveguides that were optimized for low loss and tight bending to enable compact device footprints. They were built with waveguide thickness of 300 nm, width of 360 nm and slab height of 150 nm. This waveguide structure only supports TE mode. The slab and ridge sections of the rings were intentionally doped for electrical transport with resistances of several hundred ohms. The bus waveguides were provisioned with grating couplers that facilitated optical access to the devices with low coupling losses of about 2 to 3 dB per unit.

3. Thermal tuning performance

Light from a tunable laser source was launched into the input filters’ ports via the grating couplers and their spectral response was monitored as the current was applied to the heaters. Current, voltage and the corresponding power level are accurately monitored and maintained. The 200 µm diameter ring optical performance is shown in the Fig. 3
Fig. 3 Filter transmission versus wavelength as a function of applied power to a ring MUX of 200 µm diameter.
for a variable applied electrical power and its spectral response measured. Due to the thermo-optic coefficient of silicon as the temperature increases, the silicon ring refractive index increases resulting in the shift in its resonant peak to longer wavelength. The free spectral range for the filter, shown in Fig. 3, is about 1 nm. Its resonance peak can be shifted by 2π with 82 mW of applied electrical power. The amount of wavelength (and phase) shift is observed to have a linear dependence on the electrical tuning power indicative of a linear thermo-optic effect. In our case the thermal efficiency for thermal tuning of this ring filter equates to about 80mW/nm which is consistent with the geometry of the ring.

Given the inverse dependence of thermal efficiency on ring radius identified above it may seem sensible to design WDM filters using smaller diameter rings in order to minimize the applied power for tuning a given wavelength range. Based on this sole criterion alone WDM designers would be tempted to design systems with the smallest ring radius possible to minimize overall tuning power. Nevertheless, there is another relevant tuning performance metric to consider in WDM applications which is the power required to shift a resonator within its free spectral range. To evaluate this metric we recall that the wavelength change required for a full 2π phase shift actually decreases with ring radius as follows from simple resonator theory. Combining this with the above relationship, we can further conclude that the applied power needed to tune a ring across a full 2π phase shift is actually independent of the radius of the ring. Further, this latter metric is particularly useful when combined with the cyclical or repetitive property of a filters’ frequency characteristic. For example, instead of tuning the device over multiple orders to correct shifts away from design targets it is possible to assign the laser to a higher order mode of the ring filter and then tune only over a 2π phase shift to achieve the WDM alignment. This can reduce excessive tuning power required to overcome micro fabrication errors that otherwise may need significant correction across multiple orders of the filter. Furthermore this latter metric enables comparative analysis of the ring tuning efficiencies that are actually independent of ring size. Thus we suggest a new figure-of-merit defined by the power needed for a 2π phase shift in addition to the mW/nm tuning efficiency widely used for this class of devices.

4. Co-integration of back-side etch pit

The standard 130 nm SOI-CMOS processed photonics chips [8

8. F. Gan, T. Barwicz, M. A. Popović, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kärtner, “Maximizing the Thermo-Optic Tuning Range of Silicon Photonic Structures,” IEEE Photon. Switching 67–68 (2007). [CrossRef]

,12

12. I. Shubin, “X. Zheng, H. Thacker, J. Yao, J. Costa, Y. Luo, G. Li, A. V. Krishnamoorthy, J.E. Cunningham, T. Pinguet, A. Mekis, “Thermally tunable SOI CMOS photonics circuits,” Proc. SPIE 7607, 76070C (2010). [CrossRef]

] have been thinned down to 200 µm. The back side is polished to an optical finish and PECVD coated with low stress silicon nitride layer of 300 nm thickness. This back-side nitride is selectively dry etched to pattern its surface into an array of square or rectangular openings down to silicon matching the locations of photonic resonant structures on the front-side of the chip. The nitride openings are effectively sized to accommodate for the anisotropic nature of hydroxide wet etching of silicon and to result in the undercut of designed area beneath the photonic device (Fig. 5
Fig. 5 Silicon photonic resonant structures with a substrate undercut. Top view (a) showing the heating elements and undercut area, and a respective cross-section (b) displaying the front and back side masking layers.
). The openings are aligned to [110] silicon direction.

A ring of 40 µm diameter, for example, would need a window size on the order of 400x 400 µm2 large in the back-side silicon nitride in order to achieve an undercut below the ring with ten times its respective area. A further reduced chip thickness and a substrate undercut performed with a highly directional dry etch would substantially reduce the amount of the required etched silicon substrate and make the footprint of the back-side hard mask window equal to that of the actual device on the front side.

The silicon dioxide in the SOI platform is grown stress free. Limited residual intrinsic stress is expected at that interface. Once the substrate is removed from under the resonant optical device it is situated on and supported by this stress free layer. The device carrying the silicon oxide membrane is held by the remaining silicon substrate under the rest of the circuitry where the thermal isolation is not required. The devices isolated and suspended by the undercut remain mechanically supported and stable. The described process could be readily demonstrated on the wafer level in a batch process. It is tool-compatible and chemistry-compatible with conventional back-end MEMS manufacturing.

The response time for tuning a ring with removed undercut substrate was observed to slow down relative to the unetched devices. The time required to tune the device with locally etched substrate was observed to increase approximately three times compared to the unetched rings but still measured only several microseconds for a full 2π shift.

Furthermore, the ring’s quality factor of Q = 9.6e4 remains unchanged after etching, at least to within the experimental resolution error. This implies that very little residual stress develops during the silicon handler removal process. Advantageously, due to the highly effective etch stop the internal stresses associated with non uniform and incomplete material removal can be alleviated in our fabrication approach. Otherwise these stress effects may cause strain induced inhomogeneity and local shape distortions in such a highly sensitive device with extremely high inherent Q.

The back-side etch pit can be expected to radically reduce tuning power because it disrupts heat flow spreading in the substrate of the device. This is supported by a simple analytic one-dimensional heat-flow analysis which also shows the thermal resistance of the device to decrease inversely with device diameter. A 20x reduction in the tuning has been experimentally verified and confirms expectations that thermal impedance has been drastically increased. When viewed with our simple model that scales the tuning with ring radius our result represents record performance compared with other results found in the literature [11

11. M. R. Watts, W. A. Zortman, D. C. Trotter, G. N. Nielson, D. L. Luck, and R. W. Young, “Adiabatic resonant microrings (ARMs) with directly integrated thermal microphotonics”, 2009 Conference on Lasers and Electro-Optics CLEO/QELS, CPDB10 (2009).

].

5. Conclusion

We demonstrated spectral tunability of add-drop filters manufactured as ring resonators using commercial 130 nm SOI CMOS technology. Their thermal impedance has been dramatically increased by the selective removal of the SOI handler substrate under the device footprint by co-integration with bulk silicon micromachined structures. An overall ~20x increase in the tuning efficiency has been demonstrated with a post-processed 100 µm radius ring relative to its original performance with an intact substrate.

Acknowledgements

This material is based upon work supported, in part, by DARPA under Agreement No. HR0011-08-09-000. The authors thank Dr. Jag Shah of DARPA MTO for his inspiration and support of this program. The views, opinions, and/or findings contained in this article/presentation are those of the author and should not be interpreted as representing the official views or policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the Department of Defense.

References and links

1.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009). [CrossRef]

2.

J. E. Cunningham, A. V. Krishnamoorthy, I. Shubin, X. Zheng, M. Asghari, D. Feng, and J. G. Mitchell, “Aligning Chips Face-to-Face for Dense Capacitive and Optical Communication,” IEEE Trans. Adv. Packag. 33(2), 389–397 (2010). [CrossRef]

3.

R. Soref, “The past, present, and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1678–1687 (2006). [CrossRef]

4.

C. Gunn, “CMOS photonics for high-speed interconnects,” IEEE Micro 26(2), 58–66 (2006). [CrossRef]

5.

A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007). [CrossRef]

6.

X. Zheng, P. Koka, H. Schwetman, J. Lexau, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “Silicon photonic WDM point-to-point network for multi-chip processor interconnects”, Proceedings of the 5th International Conference on Group IV Photonics, FB7, 380–382 (2008).

7.

I. Christiaens, D. Van Thourhout, and R. Baets, “Low-power thermo-optic tuning of vertically coupled microring resonators,” Electron. Lett. 40(9), 560–561 (2004). [CrossRef]

8.

F. Gan, T. Barwicz, M. A. Popović, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kärtner, “Maximizing the Thermo-Optic Tuning Range of Silicon Photonic Structures,” IEEE Photon. Switching 67–68 (2007). [CrossRef]

9.

X. Zheng, I. Shubin, G. Li, T. Pinguet, A. Mekis, J. Yao, H. Thacker, Y. Luo, J. Costa, K. Raj, J. E. Cunningham, and A. V. Krishnamoorthy, “A tunable 1x4 silicon CMOS photonic wavelength multiplexer/demultiplexer for dense optical interconnects,” Opt. Express 18(5), 5151–5160 (2010). [CrossRef] [PubMed]

10.

M. H. Khan, H. Shen, Y. Xuan, S. Xiao, and M. Qi, “Eight-Channel Microring Resonator Array with Accurately Controlled Channel Spacing”, CLEO/QELS (2008).

11.

M. R. Watts, W. A. Zortman, D. C. Trotter, G. N. Nielson, D. L. Luck, and R. W. Young, “Adiabatic resonant microrings (ARMs) with directly integrated thermal microphotonics”, 2009 Conference on Lasers and Electro-Optics CLEO/QELS, CPDB10 (2009).

12.

I. Shubin, “X. Zheng, H. Thacker, J. Yao, J. Costa, Y. Luo, G. Li, A. V. Krishnamoorthy, J.E. Cunningham, T. Pinguet, A. Mekis, “Thermally tunable SOI CMOS photonics circuits,” Proc. SPIE 7607, 76070C (2010). [CrossRef]

13.

S. Sridaran and S. A. Bhave, “Nanophotonic devices on thin buried oxide Silicon-On-Insulator substrates,” Opt. Express 18(4), 3850–3857 (2010). [CrossRef] [PubMed]

14.

P. Sun and R. M. Reano, “Submilliwatt thermo-optic switches using free-standing silicon-on-insulator strip waveguides,” Opt. Express 18(8), 8406–8411 (2010). [CrossRef] [PubMed]

15.

J. Orcutt, A. Khilo, M. Popovic, C. Holzwarth, B. Moss, H. Li, M. Dahlem, T. Bonifield, F. Kaertner, E. Ippen, J. Hoyt, R. Ram, and V. Stojanovic, “Demonstration of an Electronic Photonic Integrated Circuit in a Commercial Scaled Bulk CMOS Process,” 2008 Conference on Lasers and Electro-Optics CLEO/QELS, CTuBB3 (2008).

16.

C. Holzwarth, J. Orcutt, H. Li, M. Popovic, V. Stojanovic, J. Hoyt, R. Ram, and H. Smith, “Localized Substrate Removal Technique Enabling Strong-Confinement Microphotonics in Bulk Si CMOS Processes,” 2008 Conference on Lasers and Electro-Optics CLEO/QELS, CThKK5 (2009).

17.

N. H. Tea, V. Milanovic, C. Zincke, J. S. Suehle, M. Gaitan, M. E. Zaghloul, and J. Geist, “Hybrid Postprocessing Etching for CMOS-Compatible MEMS,” J. Microelectromech. Syst. 6(4), 363–372 (1997). [CrossRef]

18.

http://www.brewerscience.com/products/protek/wet-etch-protective-coating/

OCIS Codes
(130.3120) Integrated optics : Integrated optics devices
(130.5990) Integrated optics : Semiconductors
(130.7408) Integrated optics : Wavelength filtering devices

ToC Category:
Integrated Optics

History
Original Manuscript: June 16, 2010
Revised Manuscript: August 16, 2010
Manuscript Accepted: August 16, 2010
Published: August 23, 2010

Citation
John E. Cunningham, Ivan Shubin, Xuezhe Zheng, Thierry Pinguet, Attila Mekis, Ying Luo, Hiren Thacker, Guoliang Li, Jin Yao, Kannan Raj, and Ashok V. Krishnamoorthy, "Highly-efficient thermally-tuned resonant optical filters," Opt. Express 18, 19055-19063 (2010)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-18-18-19055


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References

  1. A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009). [CrossRef]
  2. J. E. Cunningham, A. V. Krishnamoorthy, I. Shubin, X. Zheng, M. Asghari, D. Feng, and J. G. Mitchell, “Aligning Chips Face-to-Face for Dense Capacitive and Optical Communication,” IEEE Trans. Adv. Packag. 33(2), 389–397 (2010). [CrossRef]
  3. R. Soref, “The past, present, and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1678–1687 (2006). [CrossRef]
  4. C. Gunn, “CMOS photonics for high-speed interconnects,” IEEE Micro 26(2), 58–66 (2006). [CrossRef]
  5. A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007). [CrossRef]
  6. X. Zheng, P. Koka, H. Schwetman, J. Lexau, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “Silicon photonic WDM point-to-point network for multi-chip processor interconnects”, Proceedings of the 5th International Conference on Group IV Photonics, FB7, 380–382 (2008).
  7. I. Christiaens, D. Van Thourhout, and R. Baets, “Low-power thermo-optic tuning of vertically coupled microring resonators,” Electron. Lett. 40(9), 560–561 (2004). [CrossRef]
  8. F. Gan, T. Barwicz, M. A. Popović, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kärtner, “Maximizing the Thermo-Optic Tuning Range of Silicon Photonic Structures,” IEEE Photon. Switching 67–68 (2007). [CrossRef]
  9. X. Zheng, I. Shubin, G. Li, T. Pinguet, A. Mekis, J. Yao, H. Thacker, Y. Luo, J. Costa, K. Raj, J. E. Cunningham, and A. V. Krishnamoorthy, “A tunable 1x4 silicon CMOS photonic wavelength multiplexer/demultiplexer for dense optical interconnects,” Opt. Express 18(5), 5151–5160 (2010). [CrossRef] [PubMed]
  10. M. H. Khan, H. Shen, Y. Xuan, S. Xiao, and M. Qi, “Eight-Channel Microring Resonator Array with Accurately Controlled Channel Spacing”, CLEO/QELS (2008).
  11. M. R. Watts, W. A. Zortman, D. C. Trotter, G. N. Nielson, D. L. Luck, and R. W. Young, “Adiabatic resonant microrings (ARMs) with directly integrated thermal microphotonics”, 2009 Conference on Lasers and Electro-Optics CLEO/QELS, CPDB10 (2009).
  12. I. Shubin, “X. Zheng, H. Thacker, J. Yao, J. Costa, Y. Luo, G. Li, A. V. Krishnamoorthy, J.E. Cunningham, T. Pinguet, A. Mekis, “Thermally tunable SOI CMOS photonics circuits,” Proc. SPIE 7607, 76070C (2010). [CrossRef]
  13. S. Sridaran and S. A. Bhave, “Nanophotonic devices on thin buried oxide Silicon-On-Insulator substrates,” Opt. Express 18(4), 3850–3857 (2010). [CrossRef] [PubMed]
  14. P. Sun and R. M. Reano, “Submilliwatt thermo-optic switches using free-standing silicon-on-insulator strip waveguides,” Opt. Express 18(8), 8406–8411 (2010). [CrossRef] [PubMed]
  15. J. Orcutt, A. Khilo, M. Popovic, C. Holzwarth, B. Moss, H. Li, M. Dahlem, T. Bonifield, F. Kaertner, E. Ippen, J. Hoyt, R. Ram, and V. Stojanovic, “Demonstration of an Electronic Photonic Integrated Circuit in a Commercial Scaled Bulk CMOS Process,” 2008 Conference on Lasers and Electro-Optics CLEO/QELS, CTuBB3 (2008).
  16. C. Holzwarth, J. Orcutt, H. Li, M. Popovic, V. Stojanovic, J. Hoyt, R. Ram, and H. Smith, “Localized Substrate Removal Technique Enabling Strong-Confinement Microphotonics in Bulk Si CMOS Processes,” 2008 Conference on Lasers and Electro-Optics CLEO/QELS, CThKK5 (2009).
  17. N. H. Tea, V. Milanovic, C. Zincke, J. S. Suehle, M. Gaitan, M. E. Zaghloul, and J. Geist, “Hybrid Postprocessing Etching for CMOS-Compatible MEMS,” J. Microelectromech. Syst. 6(4), 363–372 (1997). [CrossRef]
  18. http://www.brewerscience.com/products/protek/wet-etch-protective-coating/

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