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100-Gbps CMOS transceiver for multilane optical backplane system with a 1.3 cm2 footprint |
Optics Express, Vol. 19, Issue 26, pp. B777-B783 (2011)
http://dx.doi.org/10.1364/OE.19.00B777
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– Abstract
1. Introduction
2. Optical transceiver for optical backplane system
3. Fabricated CMOS optical transceiver
4. Conclusion
– References and links
– Abstract
1. Introduction
2. Optical transceiver for optical backplane system
3. Fabricated CMOS optical transceiver
4. Conclusion
– References and links
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Abstract
A compact 4 × 25 Gbps optical transceiver has been fabricated for an optical backplane system, which consists of a 4 × 25 Gbps DFB-LD array, a 4 × 25 Gbps PIN-PD array, and a CMOS transceiver chip. These are directly mounted on 9 × 14 mm2 multi-layer ceramic package with an electromagnetic shield structure to suppress inner-channel crosstalk effectively. The transceiver includes an analog front-end as well as an electrical interface function to interface with the switch LSI or CPU. Power consumption was as low as 20 mW/Gbps, and a transmission experiment was successfully conducted at 25 Gbps.
© 2011 OSA
1. Introduction
Recent rapidly grown data traffic in the information and communication networks requires a 25-Gbps short-reach (< 100 cm) interconnect backplane inside ICT equipments such as servers, routers, and storage. Optical transmission has a great potential advantage in power efficiency even at bit rates beyond 20 Gbps, as well as negligible interference between densely arranged transmission lines and connectors. For implementing optical interconnects, the optical module has to have as small a footprint and power consumption as possible. Recently, a CMOS transmitter and a receiver have been reported that incorporated vertical cavity surface emitting lasers (VCSELs), photodiodes (PDs), and packaged ICs on a common silicon carrier [1,2]. C. P. Lai et al. demonstrated full-link power-efficiency less than 8 pJ/bit at 15 Gbps. Meanwhile, F. E. Doany et al. achieved 160-Gbps bidirectional transmissions by using their transceiver module, which utilizes a 985-nm VCSEL and a photodiode 4 × 4 array flip-chip attached to a single-chip CMOS integrated circuit (IC) [3]. Also, we have developed a compact parallel optical receiver consisting of a four-channel 25-Gbps CMOS transimpedance amplifier (TIA) array and a PIN-PD array for board-to-board optical interconnects and succeed in error-free 25-Gbps signal detection with negligible crosstalk between channels [4].
F. E. Doany, C. L. Schow, C. W. Baks, D. M. Kuchta, P. Pepeljugoski, L. Schares, R. Budd, F. Libsch, R. Dangel, F. Horst, B. J. Offrein, and J. A. Kash, “160 Gb/s bidirectional polymer-waveguide board-level optical interconnects using CMOS-based transceivers,” IEEE Trans. Adv. Packag. 32(2), 345–359 (2009). [CrossRef]
We are currently focused on an optical backplane for a high-speed router as a test bed for demonstration, in which network interface (NIF) cards and a switch (SW) card are connected optically [5]. To construct an optical backplane, we have developed a compact 100 Gbps transceiver with a 9 × 14 mm2 footprint, which consists of a surface-emitting distributed feedback (DFB) laser array, a PD array, and a CMOS chip hybrid integrated onto a multi-layer ceramic package [6]. Here, we describe key technologies of the transceiver, namely, packaging and CMOS chip technology. The CMOS chip contains electrical interface (IF) circuits to convert 4 × 25 Gbps into 10 × 10 Gbps at the data rate of CPU or switch LSI inside ICT systems, as well as a laser diode driver (LDD) and TIA functions. The total power consumption is as low as 20 mW/Gbps, which is 1/5 that of the electrical backplane transmission. We conducted a transmission experiment using the module as a transmitter, and clear receiving signals at 20 Gbps and 25 Gbps were demonstrated under air-cooling conditions.
S. Nishimura, K. Shinoda, Y. Lee, G. Ono, K. Fukuda, F. Yuki, T. Takemoto, H. Toyoda, M. Yamada, S. Tsuji, and N. Ikeda, “Components and interconnection technologies for photonic-assisted routers toward green networks,” IEEE J. Sel. Top. Quantum Electron. 17(2), 347–356 (2011). [CrossRef]
T. Takemoto, F. Yuki, H. Yamashita, S. Tsuji, Y. Lee, K. Adachi, K. Shinoda, Y. Matsuoka, K. Kogo, S. Nishimura, M. Nido, M. Namiwaka, T. Kaneko, T. Sugimoto, and K. Kurata, “100 Gbps CMOS Transceiver for Multilane Optical Backplane System with a 1.3 cm Square Footprint,” in ECOC 2011, OSA Technical Digest (CD), paper Th.12.B.5, 2011.
2. Optical transceiver for optical backplane system
Figure 1
shows a block diagram of our optical module, which consists of a 4 × 25 Gbp surface emitting DFB LD array, a 4 × 25 Gbps photodiode (PD) array, and a CMOS transceiver chip all directly mounted on a 9 × 14mm2 multi-layer ceramic package. The transceiver includes an analog frontend (FE) as well as an electrical IF to interface with the SW LSI or CPU.
To construct an optical backplane system with large throughput, the optical transceiver needs to operate under air-cooling conditions inside the ICT system. However, it is difficult to design a 25-Gbps VCSEL that is operable at high-temperature. Therefore, we have developed a highly efficient 1.3-μm DFB-LD with slope efficiency of 0.29 W/A [7] and PIN-PD with a responsivity of a 0.8 A/W array [8], which are both surface emitting or receiving types integrated with a monolithic lens. These devices decrease the output optical power necessary to backplane transmission effectively. The surface emitting DFB-LD provides compact optical coupling to multi-mode fibers (MMFs) using a common PETIT© optical connector. Moreover, note that generated heat at DFB-LD is dissipated through the transceiver chip to keep LD temperature less than 65 °C.
K. Adachi, K. Shinoda, T. Kitatani, T. Fukamachi, Y. Matsuoka, T. Sugawara, and S. Tsuji, “25-Gb/s multichannel 1.3-μm surface-emitting lens-integrated DFB laser arrays,” J. Lightwave Technol. 29(19), 2899–2905 (2011). [CrossRef]
Inner-channel crosstalk is one of the main problems in multi-channel optical transceivers, especially at a high data rate with close channel separation, such as 250 μm. To reduce the crosstalk, output signals from the optical devices are connected to inputs of the CMOS chip through coplanar lines, which are sandwiched by upper and lower ground layers in addition to right-and-left ground lines inside the multi-layer ceramic package. No bonding wire is used. This structure is very effective in avoiding mutual inductive couplings between channels. Figure 2
shows the simulated 25-Gbps eye diagrams for the receiver side. The eye diagram without a shield structure is significantly degraded by large mutual inductive coupling between channels. In contrast, the eye diagram of our multi-layer structure is greatly improved by reducing the mutual inductive coupling. To evaluate the effectiveness of our packaging technology, we fabricated an optical receiver consisting of a 4 × 25 Gbps PIN-PD array and CMOS TIA array, which were flip-chip mounted on a 16-mm square ceramic multi-layer package. Clear eye openings were found for all channels. The crosstalk penalty was only 0.8 dB at the data rate of 25 Gbps [4].
Figure 3
shows the block diagram of the fully integrated transceiver chip. The chip is composed of an analog FE, 4 × 25 Gbps Serializer/Deserializer (SerDes), IF logic, and 10 × 10 Gbps SerDes, which converts 4 × 25 Gbps optical signals into 10 × 10 Gbps electrical signals. The 10- and 25-Gbps SerDes are based on our previous works [9,10]. Our transceiver provides IF functions, such as header pattern insertion and detection, de-skew, and routing, between the transceiver and the SW LSI or CPU. The 10 Gbps SerDes and the IF logic both have a power dissipation of several hundred mW. Therefore, the most important thing is to reduce the power dissipation of the 25 Gbps circuit block because it occupies more than 80% of the power in the transceiver chip. We reduce its power consumption by the following three approaches. First, we integrate the electrical IF and analog FE, i.e., the LDD and TIA, into one CMOS transceiver chip, by making 25-Gbps analog FE circuits. This enables us to eliminate the 25-Gbps electrical IO with large power consumption between the analog FE and electrical IF. Second, we maximized the use of a low-power CMOS circuit block, adopting a half-rate operation with a 12.5-GHz clock in the transmitter and a quarter-rate operation with a 6.25-GHz clock in the receiver. As a result, in a circuit block operating below 12.5 Gbps, current mode logic (CML) circuits can be replaced with CMOS circuits. Thus, we reduced the circuit operation rate while maintaining the data processing performance. The final approach is to minimize the high-speed clock distribution. To do this, we adopted a PLL with a phase rotation in each channel and achieved a low-frequency clock distribution [10].
K. Fukuda, H. Yamashita, G. Ono, R. Nemoto, E. Suzuki, N. Masuda, T. Takemoto, F. Yuki, and T. Saito, “A 12.3-mW 12.5-Gb/s complete transceiver in 65-nm CMOS Process,” IEEE J. Solid-State Circuits 45(12), 2838–2849 (2010). [CrossRef]
3. Fabricated CMOS optical transceiver
Figure 4
depicts a photograph of a 4 × 25 Gbps optical transceiver assembly. The DFB-LD array, PIN-PD array, and transceiver chip were directly mounted on the multi-layer ceramic package. The transceiver chip was fabricated in the 65-nm CMOS process and was 3.6 × 5.2 mm2. Optical signals were accessed via standard 12-MMF arrays. The fiber alignment was conducted to fit on the DFB-LD array because PIN-PD array has larger optical coupling tolerance owing to the back-side-etched aspheric microlens on an InP substrate [8]. The positional accuracy at PIN-PD array was less than ±15 μm, which was an adequate value for maintaining high optical-coupling efficiency at a 25-Gbps data rate.
Figure 5
shows a photograph of a fabricated optical CMOS transceiver. The package is as small as 9 × 14mm2. Throughput of the transceiver was 100 Gbps including 10 × 10 Gbps electrical I/O and 4 × 25 Gbps optical interfaces. The optical transceivers are set to SW and NIF boards via land grid array (LGA) sockets. This structure is suitable for a board-soldering process that does not degrade fiber array.
Table 1
summarizes the target performance of optical link. The measured optical coupling losses of LD and PD were 5 ± 1 dB and 3 ± 1 dB, respectively. The total link loss totaled 8 dB. The output optical power was 2 dBm, and the targeted receiver sensitivity was −6 dBm.
Table 1 Target performance of optical link
*1) PD responsivity: 0.8 A/W,
*2) LD slope efficiency: 0.17 − 0.292 W/A
To evaluate its TX transmission with a PRBS of 231-1 from the internal PRBS generator, the output signal from the transceiver was measured while it was linked to our previously fabricated optical receiver [4] via MMF. The 20- and 25-Gbps clear eye diagrams were observed using a digital oscilloscope as shown in Fig. 6
.
Table 2
and Fig. 7
summarize the performance and estimated power consumption. Throughput of the transceiver was 100 Gbps including the 10 × 10-Gbps electrical IOs and 4 × 25-Gbps. The analog FEs in optical devices, 25-Gbps SerDes, 10-Gbps SerDes, and IF Logic were 782 mW, 1714 mW, 200 mW, and 100 mW, respectively. The total power consumption was about 2.0 watts, which is less than 1/15 that of a CFP Multi-Source Agreement (MSA) compliant 100-Gbps Ethernet (100GbE) transceiver [11].
CFP MSA Hardware Specification, Revision 1.4, 7 June 2010, http://www.cfp-msa.org/Documents/CFP-MSA-HW-Spec-rev1-40.pdf.
4. Conclusion
We developed a 4 × 25 Gbps compact optical transceiver for an optical backplane system required in coming high-speed servers, routers, and storages. Our transceiver consists of a DFB LD array, a PIN-PD array, and a high-speed IF chip mounted on a 9 × 14 mm2 ceramic package. Optical devices, a transceiver chip that includes analog FE and electrical IF, and package structure are key features in realizing low power, high speed, and a small footprint for an optical transceiver. The power dissipation was only 20 mW/Gbps at a data rate of 25 Gbps, which is less than 1/15 that of a CFP 100GbE module. To the best of our knowledge, we have developed the first 25-Gbps multi-channel transceiver with electrical IF, which is needed to introduce optical interconnects into ICT systems.
Acknowledgments
The authors thank Prof. T. Asami of the University of Tokyo, and N. Ikeda and his colleagues at Alaxala Network Corp. for their valuable discussions. This work was supported in part by “Next-generation High-efficiency Network Device Project,” which Photonics Electronics Technology Research Association (PETRA) contracted with New Energy and Industrial Technology Development Organization (NEDO).
References and links
B. G. Lee, C. L. Schow, A. V. Rylyakov, F. E. Doany, R. A. John, and J. A. Kash, “Lower-power CMOS-Driven Transmitters and Receivers,” in OSA/CLEO/QELS 2010, CMB5, 2010. | |
C. P. Lai, C. C. L. Schow, A. V. Rylyakov, B. G. Lee, F. E. Doany, R. A. John, and J. A. Kash, “20-Gb/s Power-Efficient CMOS-Driven Multimode Links,” in OSA/OFC/NFOEC 2010, OTuQ2, 2010. | |
F. E. Doany, C. L. Schow, C. W. Baks, D. M. Kuchta, P. Pepeljugoski, L. Schares, R. Budd, F. Libsch, R. Dangel, F. Horst, B. J. Offrein, and J. A. Kash, “160 Gb/s bidirectional polymer-waveguide board-level optical interconnects using CMOS-based transceivers,” IEEE Trans. Adv. Packag. 32(2), 345–359 (2009). [CrossRef] | |
T. Takemoto, F. Yuki, H. Yamashita, Y. Lee, T. Saito, S. Tsuji, and S. Nishimura, “A compact 4 x 25-Gb/s 3.0 mW/Gb/s CMOS-based optical receiver for board-to-board interconnects,” J. Lightwave Technol. 28(23), 3343–3350 (2010). | |
S. Nishimura, K. Shinoda, Y. Lee, G. Ono, K. Fukuda, F. Yuki, T. Takemoto, H. Toyoda, M. Yamada, S. Tsuji, and N. Ikeda, “Components and interconnection technologies for photonic-assisted routers toward green networks,” IEEE J. Sel. Top. Quantum Electron. 17(2), 347–356 (2011). [CrossRef] | |
T. Takemoto, F. Yuki, H. Yamashita, S. Tsuji, Y. Lee, K. Adachi, K. Shinoda, Y. Matsuoka, K. Kogo, S. Nishimura, M. Nido, M. Namiwaka, T. Kaneko, T. Sugimoto, and K. Kurata, “100 Gbps CMOS Transceiver for Multilane Optical Backplane System with a 1.3 cm Square Footprint,” in ECOC 2011, OSA Technical Digest (CD), paper Th.12.B.5, 2011. | |
K. Adachi, K. Shinoda, T. Kitatani, T. Fukamachi, Y. Matsuoka, T. Sugawara, and S. Tsuji, “25-Gb/s multichannel 1.3-μm surface-emitting lens-integrated DFB laser arrays,” J. Lightwave Technol. 29(19), 2899–2905 (2011). [CrossRef] | |
Y. Lee, K. Nagatsuma, K. Hosomi, T. Ban, K. Shinoda, K. Adachi, S. Tsuji, Y. Matsuoka, S. Tanaka, R. Mita, T. Sugawara, and M. Aoki, “A 35-GHz, 0.8-A/W and 26-m, Misalignment Tolerance Microlens-Integrated p-i-n Photodiodes,” IEICE Trans. Electron. E 94-C, 116–119 (2010). | |
K. Fukuda, H. Yamashita, G. Ono, R. Nemoto, E. Suzuki, N. Masuda, T. Takemoto, F. Yuki, and T. Saito, “A 12.3-mW 12.5-Gb/s complete transceiver in 65-nm CMOS Process,” IEEE J. Solid-State Circuits 45(12), 2838–2849 (2010). [CrossRef] | |
G. Ono, K. Watanabe, T. Muto, H .Yamashita, K. Fukuda, N. Masuda, R. Nemoto, E. Suzuki, T. Takemoto, F. Yuki, M. Yagyu, H. Toyoda, A. Kambe, T. Saito, and S. Nishimura, “10:4 MUX and 4:10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link,” ISSCC Dig. Tech. Papers, 148–149 Feb. 2011. | |
CFP MSA Hardware Specification, Revision 1.4, 7 June 2010, http://www.cfp-msa.org/Documents/CFP-MSA-HW-Spec-rev1-40.pdf. |
OCIS Codes
(200.0200) Optics in computing : Optics in computing
(200.4650) Optics in computing : Optical interconnects
(250.3140) Optoelectronics : Integrated optoelectronic circuits
ToC Category:
Subsystems for Optical Networks
History
Original Manuscript: November 2, 2011
Manuscript Accepted: November 23, 2011
Published: December 6, 2011
Virtual Issues
European Conference on Optical Communication 2011 (2011) Optics Express
Citation
Takashi Takemoto, Fumio Yuki, Hiroki Yamashita, Shinji Tsuji, Yong Lee, Koichiro Adachi, Kazunori Shinoda, Yasunobu Matsuoka, Kenji Kogo, Shinji Nishimura, Masaaki Nido, Masahiko Namiwaka, Taro Kaneko, Takara Sugimoto, and Kazuhiko Kurata, "100-Gbps CMOS transceiver for multilane optical backplane system with a 1.3 cm2 footprint," Opt. Express 19, B777-B783 (2011)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-19-26-B777
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References
- B. G. Lee, C. L. Schow, A. V. Rylyakov, F. E. Doany, R. A. John, and J. A. Kash, “Lower-power CMOS-Driven Transmitters and Receivers,” in OSA/CLEO/QELS 2010, CMB5, 2010.
- C. P. Lai, C. C. L. Schow, A. V. Rylyakov, B. G. Lee, F. E. Doany, R. A. John, and J. A. Kash, “20-Gb/s Power-Efficient CMOS-Driven Multimode Links,” in OSA/OFC/NFOEC 2010, OTuQ2, 2010.
- F. E. Doany, C. L. Schow, C. W. Baks, D. M. Kuchta, P. Pepeljugoski, L. Schares, R. Budd, F. Libsch, R. Dangel, F. Horst, B. J. Offrein, and J. A. Kash, “160 Gb/s bidirectional polymer-waveguide board-level optical interconnects using CMOS-based transceivers,” IEEE Trans. Adv. Packag.32(2), 345–359 (2009). [CrossRef]
- T. Takemoto, F. Yuki, H. Yamashita, Y. Lee, T. Saito, S. Tsuji, and S. Nishimura, “A compact 4 x 25-Gb/s 3.0 mW/Gb/s CMOS-based optical receiver for board-to-board interconnects,” J. Lightwave Technol.28(23), 3343–3350 (2010).
- S. Nishimura, K. Shinoda, Y. Lee, G. Ono, K. Fukuda, F. Yuki, T. Takemoto, H. Toyoda, M. Yamada, S. Tsuji, and N. Ikeda, “Components and interconnection technologies for photonic-assisted routers toward green networks,” IEEE J. Sel. Top. Quantum Electron.17(2), 347–356 (2011). [CrossRef]
- T. Takemoto, F. Yuki, H. Yamashita, S. Tsuji, Y. Lee, K. Adachi, K. Shinoda, Y. Matsuoka, K. Kogo, S. Nishimura, M. Nido, M. Namiwaka, T. Kaneko, T. Sugimoto, and K. Kurata, “100 Gbps CMOS Transceiver for Multilane Optical Backplane System with a 1.3 cm Square Footprint,” in ECOC 2011, OSA Technical Digest (CD), paper Th.12.B.5, 2011.
- K. Adachi, K. Shinoda, T. Kitatani, T. Fukamachi, Y. Matsuoka, T. Sugawara, and S. Tsuji, “25-Gb/s multichannel 1.3-μm surface-emitting lens-integrated DFB laser arrays,” J. Lightwave Technol.29(19), 2899–2905 (2011). [CrossRef]
- Y. Lee, K. Nagatsuma, K. Hosomi, T. Ban, K. Shinoda, K. Adachi, S. Tsuji, Y. Matsuoka, S. Tanaka, R. Mita, T. Sugawara, and M. Aoki, “A 35-GHz, 0.8-A/W and 26-m, Misalignment Tolerance Microlens-Integrated p-i-n Photodiodes,” IEICE Trans. Electron. E94-C, 116–119 (2010).
- K. Fukuda, H. Yamashita, G. Ono, R. Nemoto, E. Suzuki, N. Masuda, T. Takemoto, F. Yuki, and T. Saito, “A 12.3-mW 12.5-Gb/s complete transceiver in 65-nm CMOS Process,” IEEE J. Solid-State Circuits45(12), 2838–2849 (2010). [CrossRef]
- G. Ono, K. Watanabe, T. Muto, H .Yamashita, K. Fukuda, N. Masuda, R. Nemoto, E. Suzuki, T. Takemoto, F. Yuki, M. Yagyu, H. Toyoda, A. Kambe, T. Saito, and S. Nishimura, “10:4 MUX and 4:10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link,” ISSCC Dig. Tech. Papers, 148–149 Feb. 2011.
- CFP MSA Hardware Specification, Revision 1.4, 7 June 2010, http://www.cfp-msa.org/Documents/CFP-MSA-HW-Spec-rev1-40.pdf .
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