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Optics Express

Optics Express

  • Editor: C. Martijn de Sterke
  • Vol. 19, Iss. 5 — Feb. 28, 2011
  • pp: 4722–4727
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Vertical chip-to-chip coupling between silicon photonic integrated circuits using cantilever couplers

Peng Sun and Ronald M. Reano  »View Author Affiliations


Optics Express, Vol. 19, Issue 5, pp. 4722-4727 (2011)
http://dx.doi.org/10.1364/OE.19.004722


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Abstract

We demonstrate vertical chip-to-chip light coupling using silicon strip waveguide cantilever couplers. The guided-wave couplers consist of silicon strip waveguides embedded within silicon dioxide cantilevers. The cantilevers deflect 90° out-of-plane via residual stress, allowing vertical light coupling between separate chips. A chip-to-chip coupling loss of 2.5 dB per connection is measured for TE polarization and 1.1 dB for TM polarization at 1550 nm wavelength. The coupling loss varies by less than ± 0.8 dB within the wavelength range from 1500 nm to 1565 nm for both polarizations. The couplers enable broadband and compact system architectures involving high speed vertical data transport between photonic integrated circuits.

© 2011 OSA

1. Introduction

In modern computer systems, the disparity between on-chip computational power and off-chip communication bandwidth is an overall performance bottleneck [1

1. D. Burger, J. R. Goodman, and A. Kägi, “Limited bandwidth to affect processor design,” IEEE Micro 17(6), 55–62 (1997). [CrossRef]

]. To improve the processor-memory interface, high speed buffering memory may be monolithically integrated with the microprocessor. Larger integrated circuits, however, demand an increase in design complexity, cost, and power consumption [2

2. A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009). [CrossRef]

]. An alternative wiring technology for metal-based electrical interconnects is optical technology from long-haul communications. It is attractive for adaptation to board-to-board, chip-to-chip, and intra-chip interconnections. The benefits of optical interconnects with respect to bandwidth, signal timing, design, and architecture are detailed in several reviews [3

3. J. W. Goodman, F. J. Leonberger, S.-Y. Kung, and R. A. Athale, “Optical interconnections for VLSI systems,” Proc. IEEE 72(7), 850–866 (1984). [CrossRef]

,4

4. D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009). [CrossRef]

].

In this paper, we demonstrate a guided-wave vertical chip-to-chip coupling scheme using silicon strip waveguide cantilever couplers. The cantilever couplers are designed and fabricated to deflect out-of-plane via thin film stress. A deflection angle of 90° enables vertical light coupling between separate chips. Optical transmission measurements are conducted to characterize coupling loss, bandwidth, and misalignment tolerance. We have achieved chip-to-chip coupling loss of 2.5 dB for TE polarization and 1.1 dB for TM polarization at 1550 nm wavelength. New broadband and compact system architectures involving high speed vertical data transport between photonic integrated circuits are envisioned.

The paper is organized as follows. Section two describes the design of the cantilever couplers for the vertical chip-to-chip coupling scheme. Section three conveys the fabrication details. Section four discusses the experimental setup and measurement results. Finally, concluding remarks are given in section five.

2. Design

A schematic of vertical coupling between photonic integrated circuits using cantilever couplers is shown in Fig. 1
Fig. 1 Schematic of vertical chip-to-chip light coupling using silicon strip waveguide cantilever couplers. The silicon strip waveguide cross-section is 450 nm × 250 nm.
. A cantilever coupler consists of a silicon strip waveguide that is embedded within a silicon dioxide thin film bilayer cantilever cladding that deflects out-of-plane because of residual stress [10

10. P. Sun and R. M. Reano, “Cantilever couplers for intra-chip coupling to silicon photonic integrated circuits,” Opt. Express 17(6), 4565–4574 (2009). [CrossRef] [PubMed]

]. The bilayer cladding consists of plasma enhanced chemical vapor deposition (PECVD) silicon dioxide and buried oxide (BOX). The out-of-plane deflection relies on the thin film stress that arises naturally from thin film deposition. The sum of mean and gradient stresses results in a spontaneous out-of-plane deflection once the waveguide is released from the substrate. The deflection angle of the out-of-plane waveguide is designed to be 90°. The waveguides direct light from the bottom chip to the top chip and vice-versa. To ease lateral misalignment tolerance, the silicon strip waveguides are terminated in inverse width tapers [11

11. T. Shoji, T. Tsuchizawa, T. Watanabe, K. Yamada, and H. Morita, “Low loss mode size converter from 0.3 µm square Si wire waveguides to singlemode fibres,” Electron. Lett. 38(25), 1669–1670 (2002). [CrossRef]

,12

12. V. R. Almeida, R. R. Panepucci, and M. Lipson, “Nanotaper for compact mode conversion,” Opt. Lett. 28(15), 1302–1304 (2003). [CrossRef] [PubMed]

]. The inverse width taper provides optical mode delocalization into the oxide cladding which functions as a microfiber. In this work, each cantilever coupler consists of a 450 nm × 250 nm cross-section silicon strip waveguide and a 40 μm long inverse width taper embedded within a cladding of cross-section equal to 4 μm × 2.1 μm. The cantilever length is 100 μm and the silicon core taper tip is 60 nm wide.

3. Fabrication

Test structures for optical characterization are fabricated on silicon-on-insulator (SOI) substrates that consist of 250 nm thick silicon on top of 1 µm thick BOX. The fabrication process is shown in Fig. 2
Fig. 2 Schematic of fabrication process: (a) initial silicon circuits, (b) deposition of the Ti/Ni mask, (c) FIB direct writing of patterns on the Ti/Ni mask, (d) reactive ion etching to release SiO2 cantilevers, (e) removal of the Ti/Ni mask, (f) thermal annealing to increase deflection angle to 90°.
. Silicon strip waveguides are defined in hydrogen silsesquioxane (HSQ) resist using electron-beam lithography. Pattern transfer to the 250 nm thick silicon is accomplished using inductively-coupled plasma (ICP) etching with Cl2/O2 chemistry. A 1.1 µm thick PECVD SiO2 top cladding is then deposited at 200 °C using non-stoichiometric SiH4/N2O chemistry. A 150 nm thick nickel layer is evaporated onto the PECVD SiO2 as a hard mask. Patterns for the cantilevers are directly written on the Ni mask using Ga+ focused ion beam (FIB) milling. A subsequent reactive ion etch with SF6/He chemistry releases the cantilevers from the silicon substrate by etching the SiO2 anisotropically and the silicon substrate isotropically with large undercut. Each cantilever cross-section is 4 µm in width and 2.1 µm in height. In each cantilever, the distance between the silicon taper tip and the cantilever SiO2 end face is designed to be 1 µm. The Ni mask is removed with HNO3 solution.

The deflection angle of as-fabricated 100 µm long cantilevers is 28°. The deflection angle may be increased by increasing the length of the cantilevers. In this work, for a given cantilever length, the deflection angle is increased by increasing the stress in the bilayer cladding. The stress in the bilayer cladding is increased by annealing the cantilevers at a temperature greater than the deposition temperature of the PECVD SiO2. When the material is annealed at the higher temperature, the non-stoichiometric PECVD SiO2 exhibits impurity release and undergoes network reconstruction [13

13. R. Charavel, B. Olbrechts, and J. P. Raskin, “Stress release of PECVD oxide by RTA,” Proc. SPIE 5116, 596–606 (2003). [CrossRef]

]. The densified PECVD SiO2 produces a decrease in film thickness and increase in stress in the SiO2 bilayer cladding, producing an increase in deflection angle of the out-of-plane waveguides.

To characterize the dependence of the PECVD SiO2 film thickness versus annealing temperature, a test sample consisting of 1.1 µm PECVD SiO2 on top of 1 µm BOX is annealed at various temperatures in a rapid thermal annealing (RTA) processor in N2 ambient for 60 seconds. The SiO2 film thickness is measured after each annealing cycle using an optical reflectometer. For comparison, a reference sample with only the thermally grown 1 µm BOX layer is annealed under similar conditions. Figure 3(a)
Fig. 3 (a) Thickness reduction versus annealing temperature of test samples consisting of PECVD SiO2/BOX bilayer film and BOX single-layer film only. (b) SEMs of the as-fabricated cantilevers and the 770 °C annealed cantilevers.
is a plot of the measured thickness reduction versus annealing temperature. The thickness reduction of the PECVD SiO2/BOX sample is approximately linear with respect to annealing temperature. No significant thickness change is observed in the sample consisting of only a BOX film. The deflection angle of 100 µm long cantilevers consisting of densified PECVD SiO2 upper cladding and BOX lower cladding is increased to 90° when annealed at 770 °C. Scanning electron micrographs (SEMs) of the as-fabricated cantilevers and the 770 °C annealed cantilevers are shown in Fig. 3(b). Two cantilevers are shown in the SEMs.

To characterize the positioning accuracy of the cantilevers, the spacing between the cantilever end-tips on the top chip are measured using SEM imaging after each high temperature annealing step. The tip-to-tip spacing changes approximately linearly at a rate of 170 nm per °C of high temperature annealing. At room temperature, network reconstruction of the PECVD SiO2 does not occur and the cantilevers are found to be stable for optical measurements.

4. Test and measurement

The chip-to-chip coupling scheme is characterized by optical transmission measurements. A schematic of the measurement setup is shown in Fig. 4(a)
Fig. 4 (a) Schematic of the measurement setup. (b) Oblique view visible light micrograph of two cantilevers on the top chip coupled to two cantilevers on the bottom chip.
. An infrared tunable laser is connected to a polarization controller which outputs linearly polarized TE or TM light. Two tapered optical fibers with tip diameters of ~2 µm are mounted on 6-axis positioning stages and connected to fiber-to-chip cantilever couplers on the bottom chip [10

10. P. Sun and R. M. Reano, “Cantilever couplers for intra-chip coupling to silicon photonic integrated circuits,” Opt. Express 17(6), 4565–4574 (2009). [CrossRef] [PubMed]

]. The top chip is mounted onto a 5-axis positioning stage with piezo-electrically driven XYZ-movement and manually driven yaw- and roll-movement. Light in the waveguide on the bottom chip is coupled to the top chip through a pair of 90° angled cantilevers, and then coupled to the bottom chip through another pair of 90° angled cantilevers. Figure 4(b) shows a visible micrograph of two cantilevers on the top chip coupled to two cantilevers on the bottom chip.The chip-to-chip coupling loss is plotted versus wavelength in Fig. 5
Fig. 5 Measured vertical chip-to-chip coupling loss versus wavelength for TE and TM polarizations. The couplers are butt-coupled.
. The chip-to-chip coupling loss is measured relative to a straight waveguide of equivalent length. At 1550 nm wavelength, the coupling loss is 2.5 dB for TE polarization and 1.1 dB for TM polarization. The coupling loss varies by less than ± 0.8 dB from 1500 nm to 1565 nm wavelength for both polarizations.

The vertical chip-to-chip coupling loss versus misalignment in the vertical direction is shown in Fig. 6(a)
Fig. 6 (a) Measured coupling loss versus vertical misalignment in the Z direction for TE and TM polarizations at 1550 nm wavelength. A vertical misalignment of 0 corresponds to butt-coupling. (b) Measured coupling loss versus lateral misalignment in X and Y directions (at 0 µm lateral misalignment, the vertical misalignment is set to 1.2 µm).
at 1550 nm wavelength. A vertical misalignment of 0 µm corresponds to butt-coupling. For 5 µm of misalignment in the vertical direction, the coupling loss increases by 5.1 dB for both TE and TM polarizations. For a vertical misalignment of 1.2 µm, the chip-to-chip coupling loss versus lateral misalignment in the X and Y directions is shown in Fig. 6(b). The chip-to-chip coupling is more sensitive to translational misalignment in X and Y directions than vertical misalignment in Z direction. Misalignment of 1 µm in the X direction introduces an additional coupling loss of 6.5 dB for TE polarization and 5.5 dB for TM polarization. Misalignment of 1 µm in the Y direction introduces an additional coupling loss of 3.3 dB for TE polarization and 2.8 dB for TM polarization.

5. Conclusion

In summary, we demonstrate vertical chip-to-chip light coupling using silicon strip waveguide cantilever couplers. Cantilever couplers that consist of silicon strip waveguides embedded at the center of silicon dioxide claddings are defined and released from the silicon substrate using electron/ion-beam lithography and dry etching. The free-standing cantilevers deflect 90° out-of-plane due to thin film stress. At 1550 nm wavelength, a chip-to-chip coupling loss of 2.5 dB per connection is measured for TE polarization and 1.1 dB for TM polarization. The coupling loss varies by less than ± 0.8 dB from 1500 nm to 1565 nm wavelength for both polarizations. For 5 µm of misalignment in the vertical direction, the coupling loss increases by 5.1 dB for both polarizations. Misalignment in the horizontal X direction of 1 µm introduces an additional coupling loss of 6.5 dB for TE polarization and 5.5 dB for TM polarization. The coupling scheme enables new system architectures for high speed communications between photonic integrated circuits on separate chips. Future challenges involve cantilever design improvements to further reduce the chip-to-chip coupling loss and to relax the misalignment tolerance. Deposition conditions for the top cladding of the cantilever may also be optimized to lower the required annealing temperature to achieve a 90° deflection.

Acknowledgement

This work was supported by the National Science Foundation (NSF).

References and links

1.

D. Burger, J. R. Goodman, and A. Kägi, “Limited bandwidth to affect processor design,” IEEE Micro 17(6), 55–62 (1997). [CrossRef]

2.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009). [CrossRef]

3.

J. W. Goodman, F. J. Leonberger, S.-Y. Kung, and R. A. Athale, “Optical interconnections for VLSI systems,” Proc. IEEE 72(7), 850–866 (1984). [CrossRef]

4.

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009). [CrossRef]

5.

X. Zheng, J. E. Cunningham, I. Shubin, J. Simons, M. Asghari, D. Feng, H. Lei, D. Zheng, H. Liang, C.-C. Kung, J. Luff, T. Sze, D. Cohen, and A. V. Krishnamoorthy, “Optical proximity communication using reflective mirrors,” Opt. Express 16(19), 15052–15058 (2008). [CrossRef] [PubMed]

6.

B. S. Rho, S. H. Hwang, J. W. Lim, G. W. Kim, C. H. Cho, and W.-J. Lee, “Intra-system optical interconnection module directly integrated on a polymeric optical waveguide,” Opt. Express 17(3), 1215–1221 (2009). [CrossRef] [PubMed]

7.

L. Schares, J. A. Kash, F. E. Doany, C. L. Schow, C. Schuster, D. M. Kuchta, P. K. Pepeljugoski, J. M. Trewhella, C. W. Baks, R. A. John, L. Shan, Y. H. Kwark, R. A. Budd, P. Chiniwalla, F. R. Libsch, J. Rosner, C. K. Tsang, C. S. Patel, J. D. Schaub, R. Dangel, F. Horst, B. J. Offrein, D. Kucharski, D. Guckenberger, S. Hegde, H. Nyikal, C.-K. Lin, A. Tandon, G. R. Trott, M. Nystrom, D. P. Bour, M. R. T. Tan, and D. W. Dolfi, “Terabus: terabit/second-class card-level optical interconnect technologies,” IEEE J. Sel. Top. Quantum Electron. 12(5), 1032–1044 (2006). [CrossRef]

8.

H. Yamada, M. Nozawa, M. Kinoshita, and K. Ohashi, “Vertical-coupling optical interface for on-chip optical interconnection,” Opt. Express 19(2), 698–703 (2011). [CrossRef] [PubMed]

9.

M. Jöhnck, B. Wittmann, and A. Neyer, “64 channel 2D POF-based optical array interchip interconnect,” J. Opt. A, Pure Appl. Opt. 1(2), 313–316 (1999). [CrossRef]

10.

P. Sun and R. M. Reano, “Cantilever couplers for intra-chip coupling to silicon photonic integrated circuits,” Opt. Express 17(6), 4565–4574 (2009). [CrossRef] [PubMed]

11.

T. Shoji, T. Tsuchizawa, T. Watanabe, K. Yamada, and H. Morita, “Low loss mode size converter from 0.3 µm square Si wire waveguides to singlemode fibres,” Electron. Lett. 38(25), 1669–1670 (2002). [CrossRef]

12.

V. R. Almeida, R. R. Panepucci, and M. Lipson, “Nanotaper for compact mode conversion,” Opt. Lett. 28(15), 1302–1304 (2003). [CrossRef] [PubMed]

13.

R. Charavel, B. Olbrechts, and J. P. Raskin, “Stress release of PECVD oxide by RTA,” Proc. SPIE 5116, 596–606 (2003). [CrossRef]

OCIS Codes
(130.3120) Integrated optics : Integrated optics devices
(200.4650) Optics in computing : Optical interconnects

ToC Category:
Integrated Optics

History
Original Manuscript: January 19, 2011
Revised Manuscript: February 17, 2011
Manuscript Accepted: February 18, 2011
Published: February 24, 2011

Citation
Peng Sun and Ronald M. Reano, "Vertical chip-to-chip coupling between silicon photonic integrated circuits using cantilever couplers," Opt. Express 19, 4722-4727 (2011)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-19-5-4722


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References

  1. D. Burger, J. R. Goodman, and A. Kägi, “Limited bandwidth to affect processor design,” IEEE Micro 17(6), 55–62 (1997). [CrossRef]
  2. A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009). [CrossRef]
  3. J. W. Goodman, F. J. Leonberger, S.-Y. Kung, and R. A. Athale, “Optical interconnections for VLSI systems,” Proc. IEEE 72(7), 850–866 (1984). [CrossRef]
  4. D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009). [CrossRef]
  5. X. Zheng, J. E. Cunningham, I. Shubin, J. Simons, M. Asghari, D. Feng, H. Lei, D. Zheng, H. Liang, C.-C. Kung, J. Luff, T. Sze, D. Cohen, and A. V. Krishnamoorthy, “Optical proximity communication using reflective mirrors,” Opt. Express 16(19), 15052–15058 (2008). [CrossRef] [PubMed]
  6. B. S. Rho, S. H. Hwang, J. W. Lim, G. W. Kim, C. H. Cho, and W.-J. Lee, “Intra-system optical interconnection module directly integrated on a polymeric optical waveguide,” Opt. Express 17(3), 1215–1221 (2009). [CrossRef] [PubMed]
  7. L. Schares, J. A. Kash, F. E. Doany, C. L. Schow, C. Schuster, D. M. Kuchta, P. K. Pepeljugoski, J. M. Trewhella, C. W. Baks, R. A. John, L. Shan, Y. H. Kwark, R. A. Budd, P. Chiniwalla, F. R. Libsch, J. Rosner, C. K. Tsang, C. S. Patel, J. D. Schaub, R. Dangel, F. Horst, B. J. Offrein, D. Kucharski, D. Guckenberger, S. Hegde, H. Nyikal, C.-K. Lin, A. Tandon, G. R. Trott, M. Nystrom, D. P. Bour, M. R. T. Tan, and D. W. Dolfi, “Terabus: terabit/second-class card-level optical interconnect technologies,” IEEE J. Sel. Top. Quantum Electron. 12(5), 1032–1044 (2006). [CrossRef]
  8. H. Yamada, M. Nozawa, M. Kinoshita, and K. Ohashi, “Vertical-coupling optical interface for on-chip optical interconnection,” Opt. Express 19(2), 698–703 (2011). [CrossRef] [PubMed]
  9. M. Jöhnck, B. Wittmann, and A. Neyer, “64 channel 2D POF-based optical array interchip interconnect,” J. Opt. A, Pure Appl. Opt. 1(2), 313–316 (1999). [CrossRef]
  10. P. Sun and R. M. Reano, “Cantilever couplers for intra-chip coupling to silicon photonic integrated circuits,” Opt. Express 17(6), 4565–4574 (2009). [CrossRef] [PubMed]
  11. T. Shoji, T. Tsuchizawa, T. Watanabe, K. Yamada, and H. Morita, “Low loss mode size converter from 0.3 µm square Si wire waveguides to singlemode fibres,” Electron. Lett. 38(25), 1669–1670 (2002). [CrossRef]
  12. V. R. Almeida, R. R. Panepucci, and M. Lipson, “Nanotaper for compact mode conversion,” Opt. Lett. 28(15), 1302–1304 (2003). [CrossRef] [PubMed]
  13. R. Charavel, B. Olbrechts, and J. P. Raskin, “Stress release of PECVD oxide by RTA,” Proc. SPIE 5116, 596–606 (2003). [CrossRef]

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