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Optics Express

Optics Express

  • Editor: C. Martijn de Sterke
  • Vol. 20, Iss. 10 — May. 7, 2012
  • pp: 11256–11270
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High speed photodiodes in standard nanometer scale CMOS technology: a comparative study

Behrooz Nakhkoob, Sagar Ray, and Mona M. Hella  »View Author Affiliations


Optics Express, Vol. 20, Issue 10, pp. 11256-11270 (2012)
http://dx.doi.org/10.1364/OE.20.011256


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Abstract

This paper compares various techniques for improving the frequency response of silicon photodiodes fabricated in mainstream CMOS technology for fully integrated optical receivers. The three presented photodiodes, Spatially Modulated Light detectors, Double, and Interrupted P-Finger photodiodes, aim at reducing the low speed diffusive component of the photo generated current. For the first photodiode, Spatially Modulated Light (SML) detectors, the low speed current component is canceled out by converting it to a common mode current driving a differential transimpedance amplifier. The Double Photodiode (DP) uses two depletion regions to increase the fast drift component, while the Interrupted-P Finger Photodiode (IPFPD) redirects the low speed component towards a different contact from the main fast terminal of the photodiode. Extensive device simulations using 130 nm CMOS technology-parameters are presented to compare their performance using the same technological platform. Finally a new type of photodiode that uses triple well CMOS technology is introduced that can achieve a bandwidth of roughly 10 GHz without any process modification or high reverse bias voltages that would jeopardize the photodetector and subsequent transimpedance amplifier reliability.

© 2012 OSA

1. Introduction

The speed of photodetectors in CMOS technology is limited by many factors. Primarily, the drop of optical absorption coefficient of silicon at near-infrared wavelengths increases the penetration depth of the light compared to the junction depth. The time taken by the deeply generated carriers to move back to the surface increases the recovery time of the photodiode. Figure 1 shows the different possible regions where light can be absorbed in a P-N junction in typical CMOS technology. The depletion region width (xaxd) in Fig. 1 decreases with the down scaling of CMOS technology as a result of increasing doping concentrations. Thus, higher percentage of the incoming photons is absorbed in regions with no electric field.

Fig. 1 Illustration of absorbed light and generated carriers in different regions of a Si-CMOS photodiode (α is absorption coefficient).

The speed of deeply generated carriers is given by vDiffusionVT2D2n, where VT is thermal voltage and Dn is the diffusion coefficient, while the speed of drift component is given by vDriftμVxaxd, where xaxd is depletion region width and V is the applied reverse bias. The speed of the diffusion component is much lower than the drift component, which puts a serious bottleneck in the achievable bandwidth for Si- photodiodes. Figure 2 shows the typical time domain and frequency response of Si-CMOS photodiodes in response to 850 nm light.

Fig. 2 Photo-generated current response of CMOS photodiodes, (a) time domain, (b) frequency domain.

As shown in Fig. 2(a), the long diffusion tail of the photo current forces a hold off time between incident light pulses, which clearly reduces the speed of communication. Figure 2(b) also shows the two roll off regions in the typical frequency response of photodiodes with the first roll off corresponding to diffusion component of photocurrent and the second roll off a result of finite transit time (τt) of carriers generated in the depletion region given by [7

7. S. B. Alexander, Optical Communication Receiver Design (SPIE Optical Engineering Press, 1997). [CrossRef]

]:
ωt=2.78τt
(1)
Where ωt /2π is the transit time bandwidth of the photodiode. In order to boost the bandwidth of the photodiode, either the reverse bias could be increased to widen the depletion region and reduce the diffusive component, or the photodiode structure could be modified to remove the diffusion component altogether. The former solution suffers from the maximum supply voltage limitation in modern CMOS technologies. Operating beyond the technology limits jeopardizes the reliability of the fabricated devices in a given technology. The second solution is modifying the device structure which can lead to a much higher bandwidth as shown in Fig. 3. Ideally, adding a complementary frequency response to the diffusive part of the original diode can completely eliminate the diffusion component as shown in Fig. 3(a). However, practically only partial compensation can be realized, as shown in Fig. 3(b), using an equalizer diode in a combined photodiode structure (original photodiode + equalizer diode). Circuit level equalization can then be employed following the transimpedance stage to extend the bandwidth further, once the combined photodiode has achieved a reasonable bandwidth, as shown in Fig. 3(c).

Fig. 3 Extending the bandwidth of photodiode by cancelling the diffusive component, (a) ideal cancellation, (b) partial cancellation through modified device structure (addition of equalizer diode), and (c) combined device and circuit level equalization.

While modifying the device structure by employing the equalizer diode will improve the speed, as seen in Fig. 3, it will also reduce the detector responsivity defined as:
=IPhotoPAbsorbed=IPhotoPShined(1R)T
(2)
Where PShined is the light power shined on the surface of the photodiode, IPhoto is the photo generated current, R is the reflection coefficient of the die surface, and T is the transmittance of the stack of dielectrics on top of the die in a given CMOS technology.

Various techniques have been proposed to address eliminating the diffusion component in standard CMOS and BiCMOS technologies. In this paper, we re-examine these techniques when implemented in the same technology node, using the same physical dimensions. Our objective is to highlight the pros and cons of each bandwidth enhancement technique and also consider the use of standard triple-well technologies to provide even higher bandwidth. The paper is organized as follows: Section 2 discusses the various techniques to mitigate the contribution of the diffusive photo carriers. Device simulations to characterize frequency response, depletion capacitance and dark current are discussed in Section 3. Section 4 presents the effect of dielectric stack and back-end metallization in typical CMOS processes on the photodetector performance. Conclusions are drawn in section 5.

2. Design techniques for high-speed photodetectors

2.1. Spatially Modulated Photodiode

Fig. 4 (a) Structure of Spatially Modulated Light (SML) detector, (b) schematic of SML and connection to the following amplifier.

As shown in Fig. 4(b), the shaded cathode conceptually works as an equalizer diode which partially boosts the overall bandwidth of the photodiode. Figure 5 shows the two dimensional current density as a result of diffusive electrons inside the substrate, and their path while getting collected by the N-Wells. As can be seen, the carriers are absorbed by both illuminated and covered N-Wells more or less equally.

Fig. 5 Contours of diffusive electron currents inside the substrate for SML photodiode, (a) electron concentration, (b) current densities.

In [10

10. J. Genoe, D. Coppee, J. H. Stiens, R. A. Vounckx, and M. Kuijk, “Calculation of the current response of the spatially modulated light CMOS detector” IEEE Trans. Electron. Dev. 48(9), 1892–1902 (2001). [CrossRef]

], it has been shown that the electron current component in the P-sub has the lowest speed among the current components of the SML photodiode and has a 3dB corner frequency given by:
f3dB2πDn3((1S)2+(1Ln)2)
(3)
Where S is the distance between the two adjacent N-Wells, Ln is the diffusion length of electrons inside the substrate and Dn is the diffusion constant. According to Eq. (3), decreasing S increases the bandwidth proportional to S−2. On the other hand, the responsivity decreases due to higher cancellation of the diffusion component.

Refereing to Fig. 4(b), SML photodiodes are best suited for differential circuit design for the subsequent transimpedance amplifier. The use of the differential topology has numerous advantages such as supply and ground noise rejection as well as higher linearity due to the suppression of even harmonics. The higher amplifier linearity prevents pulse width modulation at the output of the transimpedance amplifier, which can be an issue in recovering the transmitted data [11

11. B. Razavi, Design of Integrated Circuits for Optical Communications (McGraw Hill, USA, 2003).

].

2.2. Double photodiode

The second technique was introduced to extend the speed of photodiodes in BiCMOS technology [12

12. H. Zimmermann, K. Kieschnick, T. Heide, and A. Ghazi, “Integrated high-speed, high-responsivity Photodiode in CMOS and BiCMOS technology,” in Proceeding of the 29th. European Solid-State Device Research Conference, (Feb. 1999), 332–335.

]. As was explained earlier, carriers generated inside the depletion region have high speed due to the strength of the electric field. Thus, extending the width of the depletion region would increase the percentage of such high speed carriers and boost the bandwidth of the detector. Increasing the reverse bias voltage can be used for increasing the width of depletion region. However, this comes at the expense of sacrificing the reliability of the device given the junction breakdown limit set by the process technology parameters. Technology scaling also makes it extremely hard to increase the reverse voltage with the lowering of the DC supply voltages. Furthermore, the available bias provided by the subsequent amplifier to the photodiode is restricted by the technology supply voltage. The solution offered by the ”Double photodiode structure” is to create two vertical depletion regions, for example, the shallow P+diffusion/N-well junction and the deep N-well/P-Substrate junction as shown in Fig. 6.

Fig. 6 (a)Structure of Double PD, (b) equivalent circuit and connection to the amplifier.

In this device configuration, the lower P-sub/N-Well junction collects most of the diffusive photo-carriers, shielding the upper P+/N-Well junction from this slow component. In other words, the large number of diffusive electrons coming from substrate will be collected by the cathode and the smaller number of diffusive holes in the N-Well will be collected by the anode. Therefore the cathode current consists of the diffusive current of substrate and the N-Well, as well as the drift component of the depletion region, while the anode current consists of diffusive holes of the N-Well and the drift as shown in Fig. 6(b). Thus, the current from the cathode shows lower cut-off frequency and higher responsivity compared to the anode. Maximum speed can be achieved by connecting the cathode to the supply voltage, which is the maximum available voltage in the technology, while connecting the anode to the subsequent amplifier. Figure 7 shows the contours of electron current coming from the substrate. As can be clearly seen in the figure, this current is absorbed by the cathode and not by the anode connected to the subsequent amplifier.

Fig. 7 Contours of diffusive electrons of substrate and their path in Double PD, (a) electron concentration, (b) current densities.

Double photodiode has reported a bandwidth of 367 MHz and responsivity of 400 mA/W in response to a light with wavelength of 638 nm in 0.8 μm BiCMOS technology [12

12. H. Zimmermann, K. Kieschnick, T. Heide, and A. Ghazi, “Integrated high-speed, high-responsivity Photodiode in CMOS and BiCMOS technology,” in Proceeding of the 29th. European Solid-State Device Research Conference, (Feb. 1999), 332–335.

]. While this approach can lead to higher speeds, it can present a large capacitance to the subsequent amplifier compared to SML for the same photodiode device dimensions. The reason for such high capacitance is that the doping concentration of P+ and N-Well region is higher than the doping concentration of N-Well and P-Sub region of SML. Therefore the depletion region is narrower, which in turn increases the capacitance. The increase in capacitance makes the design of the following transimpedance amplifier more challenging and also increases the f2 noise component at the input of the amplifier. This is because the transimpedance amplifier following the photodiode is typically implemented as a shunt feedback TIA, which is simply a voltage amplifier with a feedback resistor between input and output. The amplifier’s noise is represented by a voltage noise at its input (Vn,A). Since, the photodiode is mostly a capacitive device and because the response of the photodiode to the light is a current, therefore for noise purposes, the input referred current noise is typically a measure of the amplifier noise (in,in). This current noise is given by i2n,in = V2n,A × (CPDω)2f2. As can be seen, unlike the shot noise of the photodiode which is proportional to f, this noise is proportional to f2 [11

11. B. Razavi, Design of Integrated Circuits for Optical Communications (McGraw Hill, USA, 2003).

].

2.3. Interrupted P-Finger photodiode

One solution to the large capacitance of the Double photodidoe is to reduce the P+ region, while keeping the total area of the depletion region the same using fractal structures. This type of photodetector, known as the Interrupted P-Finger photodiode was first introduced in [13

13. T. K. Woodward and A. V. Krishnamoorthy, “1 Gbit/s integrated optical detectors and receivers in commerical CMOS technologies,” IEEE J. Sel. Top. Quantum Electron. 5(2), 146–156 (1999). [CrossRef]

] and is depicted in Fig. 8(a). As in the Double photodiode, the diffusive electrons generated in the substrate is absorbed by the cathode, while diffusive holes of the N-Well is directed towards the anode, which is connected to the subsequent amplifier as shown in Fig. 8(b). The main advantage of this type of photodiode compared to the Double photodiode is its lower junction capacitance. The photodiode and circuit introduced in [13

13. T. K. Woodward and A. V. Krishnamoorthy, “1 Gbit/s integrated optical detectors and receivers in commerical CMOS technologies,” IEEE J. Sel. Top. Quantum Electron. 5(2), 146–156 (1999). [CrossRef]

] achieve data rate of 1 Gbit/s for a BER = 10−9 and responsivity of 10 to 40 mA/W, depending on the applied reverse bias allowable in the used 0.35 μm CMOS technology in response to λ = 850 nm. To reach the maximum achievable bandwidth using this photodiode, the cathode has to be connected to the supply voltage. Since in this case, the anode should be connected to the lowest possible voltage, the input of the subsequent amplifier doesn’t have to be designed with a large bias voltage. This can be advantageous for down-scaled CMOS technologies operating from lower supply voltage where voltage headroom is a serious issue in amplifier circuit design.

Fig. 8 (a) Interrupted P- Finger photodiode, (b) equivalent circuit and connection to the amplifier.

2.4. Triple well Interrupted N-Finger photodiode

The structure of the Interrupted P-Finger could be further modified by employing one of the characteristics of modern CMOS technologies, which is the availability of triple well option. To cancel out the low speed diffusion components, the photodiode can be created in the third well as shown in Fig. 9(a). The photo generated minority carriers of the substrate are collected by the Vdd contact and the diffusive holes inside the N-Well are absorbed by the ground connection of the third P-Well. Only the fraction of electrons which are generated in the last shallow P-Well are absorbed by the N+ fingers of the photodiode which are connected to the subsequent amplifier. Since the distance traveled by these carriers before being collected is shorter than previously introduced photodiodes, a higher bandwidth and much lower responsivity is expected. As shown in Fig. 9(b), this photodiode benefits from two equalizing diode and thus its response is close to the ideal case shown in Fig. 3(a).

Fig. 9 (a)Triple well Interrupted N-Finger photodiode, (b)equivalent circuit and connection to the amplifier.

Figure 10 presents the direction of movement of the diffusive electrons inside the substrate, and shows that most of these carriers are redirected away from the cathode connected to the transimpedance amplifier stage.

Fig. 10 Contours of diffusive electron current of substrate inside a Triple well Interrupted N-Finger photodiode, (a)electron concentration, (b) current densities.

3. Device simulation results

While the above mentioned techniques have been reported in both CMOS and BiCMOS technologies, they have never been compared in the same technology node to highlight their merits and challenges. In this section, SML, Double, and Interrupted P-Finger photodiodes are examined using 130nm CMOS technology parameters and a fixed device dimension of 65μm × 65μm. Such device area is compatible with the outer diameter of 65 μm multi mode fibers. Device simulations are done using MEDICI version D-2010. Doping concentration of the substrate is set at NA,sub = 5 × 1015 cm−3, NN–well = 1017 cm−3, NP–Well = 1019 cm−3. The layouts of the individual photodiodes have to follow the 130nm CMOS technology design rules in terms of N-Well and contacts spacings. For example, the distance between the two adjacent N-Wells in SML photodiode can not decrease beyond the technology limit to guarantee manufacturablity. The objective of the photodiode comparison is to investigate the different tradeoffs regarding speed, junction capacitance, dark current and responsivity. A figure of merit is introduced to compare different photodiodes. The comparison is done at λ =600nm and 850nm. These wavelengths target applications in visible light communication and short-range optical fiber communications using multi-mode fibers.

Figure 11 shows the simulation results for a SML photodiode with W = 6μm, S = 2.2μm, total size of 65μm × 65μm and N-Well depth of 2 μm in response to λ = 850 nm light. As seen in Fig. 11, while the bandwidth of the individual cathodes is in the range of few MHz representing the typical speed of a P-N junction photodiode, the bandwidth of the difference between the illuminated and shaded cathodes currents is 257 MHz. It is also worth noting that the subtraction of currents lead to a reduction in responsivity to around 50 mA/W. This reduction in responsivity is a result of the cancellation of a major part of the photo generated carriers and is consistent with reported results published in [4

4. D. Lee, J. Han, G. Han, and S. M. Park, “An 8.5 Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer,” IEEE J. Solid-State Circuits 45(12), 2861–2873 (2010). [CrossRef]

]. At λ = 600nm, though, the small penetration depth nearly removes the low speed substrate current and thus the concept of SML is not advantageous at shorter wavelengths.

Fig. 11 Frequency Response of SML photodiode (W=6 μm, S= 2.2μm), area = 65×65μm2 at λ = 850nm.

The choice of 6 μm for the N-Well width of SML is a trade off given the design rule limitation of the used 130 nm CMOS technology. As seen in Fig. 4(a), there is one substrate contact between two consecutive N-Wells. The 6 μm width provides the minimum distance between the two N-Wells and therefore the maximum bandwidth, assuming 4 N-Wells for each illuminated and shaded contacts for proof of concept of SML. Under these conditions the total active width of each cathode will be around 24 μm. The same value is maintained for other photodiodes for accurate comparison.

Figure 12 shows the simulation results at 600nm and 850nm for a Double PD with the same total dimension of 65μm × 65μm and under the same process parameters. In this simulation, referring to Fig. 6(a), LN–Well = 45μm, and LP+ = 25μm, which is close to the total width of the active region in each cathode of SML. As can be seen in Fig. 12(a), the cathode has approximately the same bandwidth of a simple P-N junction due to the low speed component of the substrate, while the anode has an increased bandwidth of 790 MHz compared to 257 MHz for the SML photodidoe with the same dimensions, in response to 850 nm light. The higher bandwidth of the Double photodiode is due to a more effective approach in collecting the low speed carriers of the bulk and for the wider available depletion region compared to SML. Referring to Fig. 12(b), the responsivity of the Double photodiode is less than SML by a factor of 3. This is again due to larger cancellation of the bulk current component. It is also worth mentioning that for shorter wavelengths, responsivity of the anode increases and bandwidth is nearly the same. The reason is that for shorter wavelengths, the penetration depth of light decreases [14

14. S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed. (John Wiley and Sons, NJ. USA, 2007).

] and thus the percentage of substrate current reduces. Therefore, less current is absorbed by the cathode and more current is available for the high speed anode. Since more diffusive currents are absorbed inside the N-Well, and given the depth of 2 μm for N-Well in the used technology, the bandwidth of the anode slightly reduces referring back to Fig. 3(b). As the diffusive electrons of the substrate are absorbed by the Vdd connection of the cathode in this simulation, the anode bandwidth is defined by the diffusive component of the N-Well and the drift component, which is nearly the same for the two wavelengths.

Fig. 12 Frequency response of Double photodiode (LN–Well = 45μm, LP+ = 25μm), with total size of 65μm × 65μm for two different wavelengths.

For the Interrupted P-Finger PD, 3 fingers are used for the simulations shown in Fig. 13. As shown in the figure, a slightly lower bandwidth compared to Double PD is obtained at λ = 850nm for the anode. The slight reduction in bandwidth is due to sub-optimal collection of the diffusive component of the substrate compared to the Double PD, and a longer distance which diffusive carriers inside the N-Well need to move before being absorbed by the P+ fingers. The simulation shows a bandwidth of 733 MHz and 575 MHz and responsivity of roughly 5.27 and 22.75 mA/W for the anode, corresponding to 850 and 600 nm wavelength respectively.

Fig. 13 Simulation results for a 3 finger Interrupted P-Finger photodiode (LN–Well = 45μm, W = 4μm, and S = 4μm), with total size of 65μm × 65μm.

The simulated frequency response of a triple well Interrupted N-Finger photodiode for a total size of 65μm × 65μm is shown in Fig. 14. The photodiode achieves a bandwidth of roughly 10 GHz while having a responsivity of 3 mA/W for λ = 850 nm. Due to a much more efficient cancellation of the diffusive carriers in this type of the photodiode compared to other photodiodes introduced in this work, the response of a Triple Well Interrupted PD is close to the ideal case shown in Fig. 3(a). The bandwidth of this photodiode is more than a factor of 2 compared to the recently published meshed SML introduced in [9

9. S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed Spatially-Modulated photo detector in .18- μm CMOS technology,” IEEE J. Solid-State Circuits 46(5), 1158–1169 (2011). [CrossRef]

], which uses a reverse bias of 14V in 180 nm CMOS technology.

Fig. 14 Simulated frequency response of a Triple-Well 3 finger Interrupted N-Finger photodiode (LN–Well = 45μm, LP–Well = 25μm, W = 3μm, and S = 1.4μm), in response to 850 and 600 nm wavelengths.

While optical bandwidth of the photodiode is mostly governed by the diffusion component of the optically generated carriers, its junction capacitance has a critical role in determining the overall bandwidth of the receiver. The device capacitance adds to the total capacitance at the input of the following transimpedance amplifier. The input transistors in the amplifier circuit are typically designed to have a large width to lower the total noise contributed by the circuit. To limit the effect of the photodiode on the bandwidth, its capacitance has to be kept as low as possible. On the other hand, to minimize the noise at the input of the receiver, capacitance of the photodiode should be designed to be equal to the input capacitance of the subsequent amplifier. The junction capacitance of the three discussed photodetectors is calculated using the 130nm CMOS technology parameters under a given reverse bias voltage of 1.2 V, which is the nominal supply voltage in this technology. For capacitance calculations, the junction curvature and proximity by the surrounding isolation or near FET devices are included in the process parameters and model equations. The 65 × 65 μm2 SML photodiode with 4 N-Well on each cathode gives a capacitance of around 1.32 pF. For the same process parameters, the Double photodiode has a capacitance of 1.54 pF for an anode size of 25 × 65 μm2. The higher capacitance of the Double photodiode is due to higher doping concentration of anode and cathode compared to SML. For the Interrupted P-Finger photodiode, the capacitance equals 775 fF. The reason for this decrease is that the side wall capacitance of the P+ region has much less contribution to the total capacitance of the P+/NWell, as the depth of the P+ region is around 0.3 μm and the width of each finger is 4 μm. The bottom area capacitance of the Interrupted photodiode is less than Double because it consists of fingers and is not thorough compared to Double photodiode. For the Triple-well Interrupted photodiode, referring to Fig. 9(a) and assuming the same active area width of LP–well = 25 μm, each finger in this photodiode has a width of 3 μm which is smaller than the fingers of the Interrupted P-Finger photodiode. Therefore the capacitance of the Triple Well Interrupted PD is smaller than the Interrupted P-Finger PD. The calculated capacitance for this design is 645 fF.

Another photodiode parameter which affects the noise performance of the device is the dark current, typically known as reverse bias leakage current. Since the leakage current passes through the barrier potential of the junction, it has a shot noise associated with it with spectral density defined by
In2=2qIDarkΔf
(4)
Where In2 is power spectral density (PSD) of the shot noise, q is the unit electron charge, IDark is the reverse bias current under no illumination condition, and Δf is the frequency bandwidth. Given that SML has the least doping concentration in its anode/cathode compared to other photodiodes, a higher dark current is expected. Also, the Triple Well Interrupted photodiode will have the least leakage due to the highest doping concentration in its anode/cathode. For comparison purposes, a Figure of Merit (FOM) is defined for the photodiodes to combine their performance parameters such as junction capacitance, leakage current, bandwidth and responsivity as well as the used technology node. As has been discussed in [6

6. F. Tavernier and M. S. J. Steyaert, “High speed optical receivers with integrated photodiode in 130 nm CMOS,” IEEE J. Solid-State Circuits 44(10), 2856–2867 (2009). [CrossRef]

], the technology contribution must be squared because of the effect of higher doping concentration, which increases the junction capacitance as well as the number of dielectric stacks on top of the die, which attenuates the light. The main effect of the dark current is its shot noise which has a white spectrum as shown in Eq. (4), and therefore extends to high frequencies. Hence it degrades the signal to noise ratio at the input of the optical receiver. Clearly, a higher responsivity and wider bandwidth are advantageous, while less capacitance and lower dark current are not. Consequently, the FOM can be defined as:
FOM=(R[mAW]×B.W.[MHz]C[PF]×ILeakage[pA]×(Technology2[nm2]))×1000
(5)

Where R is the responsivity and C is the capacitance of the photodiode, while Technology is the minimum length of the used CMOS technology node. Table 1 summarizes the different performance parameters of the previously discussed photodetectors under a reverse bias of 1.2V for the given 130 nm CMOS technology.

Table 1. Performance parameters comparison of high speed CMOS photodiodes.

table-icon
View This Table

As can be seen in Table 1, both Double and Interrupted P-Finger PD have a FOM higher than SML. The Double photodidoe is particularly interesting because it provides more than 3 times bandwidth compared to SML, and a dark current less than half of SML. The downside is its lower responsivity which is around one third of SML. The large FOM of Triple Well Interrupted N-Finger is due to its wide bandwidth and small dark current as a result of using junctions with higher doping concentrations.

4. The optical transmission coefficient

Light travelling through a stack of materials suffers from reflection and refraction at the boundaries as well as attenuation. The situation gets worse in each newer generation of CMOS technology, because the number of metal and dielectric layers increases. For example, in 130 nm CMOS technology, there are 8 levels of metals, and thus eight levels of dielectric stack, while 90 nm CMOS has nine levels of metals and nine dielectric layers. In addition to these dielectric layers, there is a final passivation on top of the last metal layer, which adds up to the total stack. Shown in Fig. 15, this stack has a serious effect on the responsivity of the photodiodes fabricated in modern CMOS technologies.

Fig. 15 General structure of 130 nm technology with Back end of line metallization and dielectric stack.

The fraction of the light which passes through this dielectric stack and reaches the surface of the photodiode is called Transmittance. The simulated transmittance ;(using Medici); of the light while passing through the stack of the dielectric layers in the used 130 nm CMOS technology, is plotted versus wavelength in Fig. 16. Also, effect of process variation on the transmittance is shown in the same figure. As can be seen, the Transmittance is a highly nonlinear function of the wavelength, with typical value around 85% for λ = 850 nm wavelength, and roughly 70 % for λ = 600 nm.

Fig. 16 Transmittance of light passing through the stack of dielectric layers in 130 nm IBM CMOS technology with ±20% process variation in thickness of layers.

5. Conclusions

This paper summarizes various techniques to improve the low inherent bandwidth of standard CMOS photodiodes, as well as propose a new technique for improving the speed of the photodiode. Device simulations in 130 nm CMOS technology show an optical bandwidth of 257MHz, 794MHz, 733MHz, and 9.67GHz with responsivity of 47.5, 17.6, 5.3, and 2.3 mAW for SML, Double, Interrupted P-Finger and Triple well Interrupted N-Finger photodiode respectively, in response to the light with wavelength of 850 nm. Also, junction capacitance of the presented photodiodes for a nominal bias of 1.2 Volts as well as their corresponding dark currents are reported. The introduced photodiodes can provide at least 2.5 times higher bandwidth compared to the widely used SML photodiode, and would prove to be practical for CMOS implementation of existing and evolving optical communication applications.

Acknowledgments

This work is supported by NSF under grants EEC-0812056, CNS-0721612 and NYSTAR contract C090145.

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13.

T. K. Woodward and A. V. Krishnamoorthy, “1 Gbit/s integrated optical detectors and receivers in commerical CMOS technologies,” IEEE J. Sel. Top. Quantum Electron. 5(2), 146–156 (1999). [CrossRef]

14.

S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed. (John Wiley and Sons, NJ. USA, 2007).

OCIS Codes
(060.0060) Fiber optics and optical communications : Fiber optics and optical communications
(130.0130) Integrated optics : Integrated optics
(230.0230) Optical devices : Optical devices
(250.0250) Optoelectronics : Optoelectronics

ToC Category:
Fiber Optics and Optical Communications

History
Original Manuscript: January 4, 2012
Revised Manuscript: March 9, 2012
Manuscript Accepted: April 2, 2012
Published: May 2, 2012

Citation
Behrooz Nakhkoob, Sagar Ray, and Mona M. Hella, "High speed photodiodes in standard nanometer scale CMOS technology: a comparative study," Opt. Express 20, 11256-11270 (2012)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-20-10-11256


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References

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  8. D. Coppee, M. Kuijk, and R. Vounckx, “Spatially modulated light detector in CMOS with sense-amplifier receiver operating at 180 Mb/s for optical data link applications and parallel optical interconnects between chips,” IEEE J. Sel. Top. Quantum Electron.4(6), 1040–1045 (1998). [CrossRef]
  9. S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed Spatially-Modulated photo detector in .18- μm CMOS technology,” IEEE J. Solid-State Circuits46(5), 1158–1169 (2011). [CrossRef]
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  11. B. Razavi, Design of Integrated Circuits for Optical Communications (McGraw Hill, USA, 2003).
  12. H. Zimmermann, K. Kieschnick, T. Heide, and A. Ghazi, “Integrated high-speed, high-responsivity Photodiode in CMOS and BiCMOS technology,” in Proceeding of the 29th. European Solid-State Device Research Conference, (Feb. 1999), 332–335.
  13. T. K. Woodward and A. V. Krishnamoorthy, “1 Gbit/s integrated optical detectors and receivers in commerical CMOS technologies,” IEEE J. Sel. Top. Quantum Electron.5(2), 146–156 (1999). [CrossRef]
  14. S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed. (John Wiley and Sons, NJ. USA, 2007).

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