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Optics Express

Optics Express

  • Editor: C. Martijn de Sterke
  • Vol. 20, Iss. 11 — May. 21, 2012
  • pp: 12222–12232
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Open foundry platform for high-performance electronic-photonic integration

Jason S. Orcutt, Benjamin Moss, Chen Sun, Jonathan Leu, Michael Georgas, Jeffrey Shainline, Eugen Zgraggen, Hanqing Li, Jie Sun, Matthew Weaver, Stevan Urošević, Miloš Popović, Rajeev J. Ram, and Vladimir Stojanović  »View Author Affiliations


Optics Express, Vol. 20, Issue 11, pp. 12222-12232 (2012)
http://dx.doi.org/10.1364/OE.20.012222


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Abstract

This paper presents photonic devices with 3 dB/cm waveguide loss fabricated in an existing commercial electronic 45 nm SOI-CMOS foundry process. By utilizing existing front-end fabrication processes the photonic devices are monolithically integrated with electronics in the same physical device layer as transistors achieving 4 ps logic stage delay, without degradation in transistor performance. We demonstrate an 8-channel optical microring-resonator filter bank and optical modulators, both controlled by integrated digital circuits. By developing a device design methodology that requires zero process infrastructure changes, a widely available platform for high-performance photonic-electronic integrated circuits is enabled.

© 2012 OSA

1. Introduction

2. CMOS foundry integration methodology

The photonic devices, including dense wavelength division multiplexing (DWDM) filters and electro-optic modulators, are patterned in the standard process using available design layers traditionally used for transistor fabrication. Photonic devices were fabricated in the standard processing flow of the IBM 12SOI 45 nm SOI-CMOS foundry alongside 3-million transistors. The design was submitted for mask aggregation at the Kansas City Plant (KCP) as part of a Trusted Access Program Office (TAPO) shuttle run. Physical process details, including the cross-sectional layer type and thickness information explicitly not reported in this work, are provided as part of the standard electronic design kit that is made available to IBM foundry customers under a non-disclosure agreement. A subset of process and performance information regarding this electronics process can be found in IBM publications [10

10. S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Yu, S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Warm, T. Ivers, and P. Agnello, “High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography,” in International Electron Devices Meeting (IEEE, 2006), 1–4.

,15

15. R. Kalla, B. Sinharoy, W. J. Starke, and M. Floyd, “Power7: IBM's next-generation server processor,” IEEE Micro 30(2), 7–15 (2010). [CrossRef]

,16

16. L. Sungjae, B. Jagannathan, S. Narasimha, A. Chou, N. Zamdmer, J. Johnson, R. Williams, L. Wagner, K. Jonghae, J. O. Plouchart, J. Pekarik, S. Springer, and G. Freeman, “Record RF performance of 45-nm SOI CMOS Technology,” in Electron Devices Meeting (IEEE 2007), 255–258.

].

Design preparation was performed in Cadence Virtuoso and Encounter tools to enable electronic-photonic integration and compliant design submission [17

17. J. S. Orcutt and R. J. Ram, “Photonic device layout within the foundry CMOS design environment,” IEEE Photon. Technol. Lett. 22(8), 544–546 (2010). [CrossRef]

]. Local pattern density process compliance was maintained in mask design while excluding optically-lossy metals from a 2-3 μm region around the waveguides [17

17. J. S. Orcutt and R. J. Ram, “Photonic device layout within the foundry CMOS design environment,” IEEE Photon. Technol. Lett. 22(8), 544–546 (2010). [CrossRef]

]. Custom auto-fill routines were developed to identify design coordinates requiring fill to meet pattern density targets using a script written for Mentor Graphics Calibre. High-density, 0.8 μm x 0.8 μm, metal fill cells were then automatically inserted at these design coordinates using scripts developed inside Cadence Virtuoso. Several waivers for violations of standard process design rules were obtained through the standard foundry infrastructure. Most resulted from photonic devices being erroneously flagged during the automated design rule check processing as improperly formed electronic devices. The smooth photonic shapes such as rings and bends were discretized onto the allowed mask address grid and represented in the submitted database as many rectangles [17

17. J. S. Orcutt and R. J. Ram, “Photonic device layout within the foundry CMOS design environment,” IEEE Photon. Technol. Lett. 22(8), 544–546 (2010). [CrossRef]

]. Geometry waivers for the small, nanometer-scale notches formed by this discretization were also obtained, as these shapes have been shown to present no structural threat to process yield in several process generations from multiple manufacturers [9

9. J. S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popović, H. Li, J. Sun, T. Bonifield, R. Hollingsworth, F. X. Kärtner, H. I. Smith, V. Stojanović, and R. J. Ram, “Nanophotonic integration in state-of-the-art CMOS foundries,” Opt. Express 19(3), 2335–2346 (2011). [CrossRef] [PubMed]

, 17

17. J. S. Orcutt and R. J. Ram, “Photonic device layout within the foundry CMOS design environment,” IEEE Photon. Technol. Lett. 22(8), 544–546 (2010). [CrossRef]

19

19. J. S. Orcutt, “Scaled CMOS photonics,” in Photonics in Switching (Optical Society of America, 2010), PMC4.

].

Electronic ring oscillators, formed by an odd number of inverting logic stages and placed in close proximity of the photonic devices in the photonic integration regions, indicate no observable transistor performance degradation verifying that photonic devices can be integrated closely with high-performance transistors. The logic stage delay characterized by the oscillator resonant frequency is shown in Fig. 2
Fig. 2 Plot of measured logical stage delay for ring oscillators both before and after substrate transfer (described in Section 3) as a function of supply voltage. The nominal supply voltage for this process is 1V. The delay is extracted by dividing the measured oscillation frequency by the number of stages.
. The achieved switching time of less than 5 ps is the fastest demonstration of logic transistor performance within a monolithically integrated photonic platform [16

16. L. Sungjae, B. Jagannathan, S. Narasimha, A. Chou, N. Zamdmer, J. Johnson, R. Williams, L. Wagner, K. Jonghae, J. O. Plouchart, J. Pekarik, S. Springer, and G. Freeman, “Record RF performance of 45-nm SOI CMOS Technology,” in Electron Devices Meeting (IEEE 2007), 255–258.

].

3. Substrate-transfer post-processing

Since the SOI-CMOS electronics process is optimized for transistor performance and low thermal impedance, the buried oxide (BOX) layer that separates the silicon layer from the handle wafer is thinner than 200 nm as shown in Fig. 3
Fig. 3 Cross section cartoon of photonic integration within a scaled thin-SOI platform. The single-crystalline silicon waveguide core (body-Si) is formed in the layer that functions as the transistor body in the standard electronics process. The polysilicon (poly-Si) waveguide core is formed in the layer that functions as the transistor gate in the standard electronics process. The proximity of the two layers enables the formation of a strip-loaded waveguide as well.
. This is in contrast to the 2-3 μm buried oxide thickness that is common for photonics SOI wafers. The as-fabricated wafers therefore do not provide sufficient low-index cladding thickness underneath the silicon waveguide core to eliminate substrate leakage loss. Post-processing that can locally remove the underlying silicon has been demonstrated previously for various photonics applications [9

9. J. S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popović, H. Li, J. Sun, T. Bonifield, R. Hollingsworth, F. X. Kärtner, H. I. Smith, V. Stojanović, and R. J. Ram, “Nanophotonic integration in state-of-the-art CMOS foundries,” Opt. Express 19(3), 2335–2346 (2011). [CrossRef] [PubMed]

,20

20. S. Sridaran and S. A. Bhave, “Nanophotonic devices on thin buried oxide Silicon-On-Insulator substrates,” Opt. Express 18(4), 3850–3857 (2010). [CrossRef] [PubMed]

,21

21. P. Dong, W. Qian, H. Liang, R. Shafiiha, N.-N. Feng, D. Feng, X. Zheng, A. V. Krishnamoorthy, and M. Asghari, “Low power and compact reconfigurable multiplexing devices based on silicon microring resonators,” Opt. Express 18(10), 9852–9858 (2010). [CrossRef] [PubMed]

] as well as for commercial volume production of MEMS [13

13. Akustica, “Technology,” retrieved February 7, 2012, http://www.akustica.com/Technology.asp.

]. For faster characterization turnaround, in this work we instead use a substrate-transfer process. The die received from the foundry were mounted pad-side down to an oxidized silicon wafer with Crystalbond 509. The exposed silicon substrate of the die was then removed using 10 s etch, 50 s pump cycles of XeF2 gas. Once the substrate is completely removed, a thermally and electrically conductive transfer substrate of 6H-SiC is bonded to the CMOS layer stack using Norland Optical Adhesive 71. This optically clear adhesive with a working temperature of 125 °C is UV cured in place and aged in a 50 °C oven for 12 h. Next, the transferred die is removed from the handle wafer by melting the Crystalbond on a 85 °C hot plate. After cleaning, the transferred die is wire bonded into a 208-pin ceramic pin-grid array package (Spectrum CPG20809). The received packaged samples were then used in the optoelectronic characterization experiments. After all post-processing is completed, we verify that the integrated transistor characteristics remain within 5% of their as-fabricated state at nominal supply voltage by re-measuring the ring oscillator after transfer as shown in Fig. 2. Similar experiments to verify that wafer-scale, front-side localized substrate removal post-processing does not impact transistor characteristics have been reported in the post-CMOS MEMS literature [14

14. C.-L. Dai, F.-Y. Xiao, Y.-Z. Juang, and C.-F. Chiu, “An approach to fabricating microstructures that incorporate circuits using a post-CMOS process,” J. Micromech. Microeng. 15(1), 98–103 (2005). [CrossRef]

].

4. Waveguide loss characterization

The low waveguide loss of the single crystalline silicon layer, comparable with the state-of-the-art for most wavelengths, enables the fabrication of highly-efficient resonant photonic devices. Extracted intrinsic quality factors of 227,000 and 112,000 were obtained for 1280 nm and 1550 nm rings respectively as shown in Fig. 4(c) and 4(d). The corresponding waveguide losses are calculated to be 3.7 dB/cm and 4.6 dB/cm by using group indices of 3.92 and 2.94 as calculated from the free spectral ranges for 1280 nm and 1550 nm light respectively. In addition to confirming the order of magnitude of the waveguide losses measured by the paperclips, the resonator quality factor measurements confirm that the curved waveguide mode present in the ring also exhibits low propagation loss.)

5. Wavelength division multiplexing filter banks

The high-resolution photolithography used in this 45 nm process enables the precise lateral dimension control that is critical to a wide variety of photonic devices [9

9. J. S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popović, H. Li, J. Sun, T. Bonifield, R. Hollingsworth, F. X. Kärtner, H. I. Smith, V. Stojanović, and R. J. Ram, “Nanophotonic integration in state-of-the-art CMOS foundries,” Opt. Express 19(3), 2335–2346 (2011). [CrossRef] [PubMed]

, 22

22. F. N. Xia, L. Sekaric, and Y. Vlasov, “Ultracompact optical buffers on a silicon chip,” Nat. Photonics 1(1), 65–71 (2007). [CrossRef]

-23

23. S. K. Selvaraja, P. Jaenen, W. Bogaerts, D. V. Thourhout, P. Dumon, and R. Baets, “Fabrication of photonic wire and crystal circuits in silicon-on-insulator using 193-nm optical lithography,” J. Lightwave Tech. 27(18), 4076–4083 (2009). [CrossRef]

]. An important example of such a device is the ring resonator filter bank that enables the bandwidth-density advantage of silicon-photonics for interconnect applications by enabling dense wavelength division multiplexing (DWDM) [21

21. P. Dong, W. Qian, H. Liang, R. Shafiiha, N.-N. Feng, D. Feng, X. Zheng, A. V. Krishnamoorthy, and M. Asghari, “Low power and compact reconfigurable multiplexing devices based on silicon microring resonators,” Opt. Express 18(10), 9852–9858 (2010). [CrossRef] [PubMed]

, 26

26. D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009). [CrossRef]

-27

27. M. Georgas, J. Leu, B. Moss, S. Chen, and V. Stojanovic, “Addressing link-level design tradeoffs for integrated photonic interconnects,” in Custom Integrated Circuits Conference (IEEE, 2011), 1–8.

]. In the design of the filter banks presented, the target resonant frequency of each channel is not designed to a fixed absolute value due to the uncertainty in the fabricated silicon layer thickness and ambient temperature during operation. Instead, the eight channels are designed to be evenly distributed across the free spectral range (FSR) of a single filter. The fabrication precision allows the measured 8-channel filter bank, shown in Fig. 5(a)
Fig. 5 (a) Optical micrograph of an 8-channel filter bank implemented with 7.0 μm nominal radius first-order ring-resonator filters. Design dimensions: 470 nm ring and bus waveguide widths, 217 nm input and drop side ring-bus coupling gaps. (b) Filter bank transfer function for all ports as measured for fiber-to-fiber transmission.
, to be composed of evenly distributed channels by increasing the ring radius in steps of 12 nm. The as-fabricated filter transmission characteristics, shown in Fig. 5(b), verify channels distributed throughout the FSR in order, yielding no gaps or perturbations in the wavelength grid. The on-resonance filter drop loss is

measured to be less than 1 dB for all channels. The measured 10 dB fiber-to-fiber loss is dominated by expected theoretical loss of the simple vertical grating coupler designs used in this initial work.

6. Integrated electro-optic transmitters

As shown in Fig. 1, each digital backend cell in the integration test platform includes a locally driven optical modulator and photodiodes connected to data [29

29. M. Georgas, J. Orcutt, R. J. Ram, and V. Stojanovic, “A monolithically-integrated optical receiver in standard 45-nm SOI,” in European Solid State Circuits Conference (IEEE, 2011), 407–410.

] and clock receivers [30

30. J. Leu and V. Stojanovic, “Injection-locked clock receiver for monolithic optical link in 45nm SOI,” in Asian Solid State Circuits Conference (IEEE, 2011), 149–152.

]. Due to a lack of a priori process knowledge, detectors primarily served as test structures for both material characterization and understanding circuit integration for this chip. Measurements of the epitaxial SiGe material, which is present in the process for transistor strain engineering [16

16. L. Sungjae, B. Jagannathan, S. Narasimha, A. Chou, N. Zamdmer, J. Johnson, R. Williams, L. Wagner, K. Jonghae, J. O. Plouchart, J. Pekarik, S. Springer, and G. Freeman, “Record RF performance of 45-nm SOI CMOS Technology,” in Electron Devices Meeting (IEEE 2007), 255–258.

] and is the intended absorber for detector designs, demonstrated 0.5 dB/μm excess absorption at 1240 nm when compared to similarly-sized, silicon-only waveguides, projecting ~20 μm linear detector length. First-generation detectors are ~1% efficient due to extrinsic losses and are not reported in detail in this work. The below 1300 nm operating wavelengths of the modulator and filter bank presented in this paper were chosen for eventual interaction with future generations of these silicon germanium detectors.

The resonant optical modulators driven by the integrated electronics were implemented using the strip-loaded (rib) waveguide geometry shown in Fig. 6(b). The lateral p-i-n diode that is used for carrier-plasma modulation in forward-bias was formed in the single-crystalline silicon layer using the front-end doping and contact steps present for transistor fabrication. Ring resonators, shown in inset to Fig. 7(a)
Fig. 7 Resonant electro-optic modulators were demonstrated using rib waveguide, carrier-injection phase shifters. (a) The optical transmission spectra with inset micrographs are shown for the 1280 nm (Q = 3970) and 1550 nm (Q = 4290) wavelength bands. The silicon slab layers are continuous in the coupling regions and 132 nm gaps and 122 nm gaps are formed between the polysilicon strips for the 1280 nm and 1550nm designs respectively. Cross-section cartoon of the 1550 nm device is shown in (b) to illustrate the lateral optical mode confinement, contours, and electrical contact regions. The eye diagram (c) demonstrates 600 Mbps data transmission with 10 dB on-off extinction ratio for the 1550 nm modulator integrated with a modulator driver. The step function time constant dependence on driver configuration (d) demonstrates the acceleration of carrier depletion under reverse bias, but at the expense of the carrier-injection time constant in the current integrated driver configuration for a 1280 nm modulator. The measured small-signal modulation electro-optic transfer response for a 1550 nm modulator is shown in (e) with the injection current as a function of diode bias voltage shown in inset for both modulators (1550 nm device in blue, 1280 nm in red).
, formed using the plasma-modulating rib waveguides function as amplitude modulators by tuning the resonance on and off resonance relative to the incoming laser frequency [31

31. Q. Xu, B. Schmidt, S. Pradhan, and M. Lipson, “Micrometre-scale silicon electro-optic modulator,” Nature 435(7040), 325–327 (2005). [CrossRef] [PubMed]

]. Since the optical mode is confined sufficiently far away from the optically-lossy contacts, the resonators’ FWHM optical bandwidths were measured to be 60 GHz near 1260 nm and 45 GHz near 1550 nm as shown in Fig. 7(a). Accurate fabrication enabled close to critical-coupling of the modulators with 9 dB and 10 dB on-resonance extinctions near 1260 nm and 1550 nm respectively.

Low series resistance enables significant carrier injection at scaled-CMOS compatible voltages as shown in the inset of Fig. 7(e). Relying on carrier injection limits the modulation rates by the time constants for diffusion and recombination within the diode. The small signal bandwidth of the modulator was measured in a copy of the circuit-connected device that was accessible with 100 μm pitch ground-signal-ground pads. An Anritsu M3692B microwave synthesizer was input through a Picosecond Pulse Labs 5542 bias tee with 0.9 V forward bias and a 50 Ohm terminated (Midwest Microwave TRM-2106-MF-SMA-02) ground-signal- ground probe (Cascade Microtech i40-GSG-100). The resulting modulated power in the optical output was measured on a HP 70900B microwave spectrum analyzer with an internal optical frontend (HP 70810B). For the fabricated modulators, the measured small-signal bandwidth is below 1 GHz as shown in Fig. 6(e), consistent with carrier-injection modulators in non-integrated processes [31

31. Q. Xu, B. Schmidt, S. Pradhan, and M. Lipson, “Micrometre-scale silicon electro-optic modulator,” Nature 435(7040), 325–327 (2005). [CrossRef] [PubMed]

].

Next, the integrated modulator driver was used to transmit data generated by the on-chip pseudo-random bit sequence (PRBS) generator shown schematically in Fig. 1. The generated eye diagram, shown in Fig. 7(c), demonstrates 10 dB on-off extinction in the resulting data stream. The integrated driver was designed as a configurable, all-digital, split-supply push-pull circuit with the schematic shown in Fig. 8
Fig. 8 Configurable, all-digital modulator driver circuit with split supplies and sub-bit pre-emphasis. The final driver stage utilizes split-supply to decouple increased modulator supply voltage from backend digital circuit supply to maintain backend circuit performance for various modulator supply conditions. Configurable forward and reverse bias drive strengths support a variety of modulator device designs on this platform.
. The integrated driver therefore allows for the electrical drive waveform to be switched from a zero-bias off-state, dominated by recombination, to a reverse-bias off-state, aided by drift-dominated carrier sweep-out, resulting in the output optical waveforms shown in Fig. 7(d). The optical eye diagram and step response were measured at 1550 nm on an Agilent 81600D sampling oscilloscope with a 30 GHz input bandwidth optical interface. The out-coupled signal from the chip was first amplified using an erbium doped fiber amplifier with the amplified spontaneous emission filtered using a band-pass filter. Due to the injection time constant and limitations of a single-polarity sub-bit pre-emphasis implemented in this chip, the achieved modulation rate in both wavelength bands is limited to 600 Mb/s achieved with a zero-bias off-state drive waveform. Further biasing and drive waveform optimization may raise the data rate well above 1 Gb/s for similar injection-based modulators by strong injection pre-emphasis [32

32. Q. Xu, S. Manipatruni, B. Schmidt, J. Shakya, and M. Lipson, “12.5 Gbit/s carrier-injection-based silicon micro-ring silicon modulators,” Opt. Express 15(2), 430–436 (2007). [CrossRef] [PubMed]

]. Alternatively, the inherent speed limitation of carrier-injection-based designs may be overcome while improving energy efficiency by modulating the depletion-region width of a pn-junction formed with intermediate doping levels available in the process [33

33. F. Liu, D. Patil, J. Lexau, P. Amberg, M. Dayringer, J. Gainsley, H. F. Moghadam, Z. Xuezhe, J. E. Cunningham, A. V. Krishnamoorthy, E. Alon, and R. Ho, “10 Gbps, 530 fJ/b optical transceiver circuits in 40 nm CMOS,” in Symposium on VLSI Circuits (IEEE, 2011), 290–291.

, 34

34. M. R. Watts, W. A. Zortman, D. C. Trotter, R. W. Young, and A. L. Lentine, “Vertical junction silicon microdisk modulators and switches,” Opt. Express 19(22), 21989–22003 (2011). [CrossRef] [PubMed]

].

7. Conclusions

Acknowledgments

This work was funded by DARPA award W911NF-10-1-0412, and also in part by the NSF, the FCRP IFC, MIT CICS, and the Trusted Foundry. The views expressed are those of the authors and do not reflect the official policy or position of the Department of Defense or theU.S. Government.

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F. N. Xia, L. Sekaric, and Y. Vlasov, “Ultracompact optical buffers on a silicon chip,” Nat. Photonics 1(1), 65–71 (2007). [CrossRef]

23.

S. K. Selvaraja, P. Jaenen, W. Bogaerts, D. V. Thourhout, P. Dumon, and R. Baets, “Fabrication of photonic wire and crystal circuits in silicon-on-insulator using 193-nm optical lithography,” J. Lightwave Tech. 27(18), 4076–4083 (2009). [CrossRef]

24.

M. A. Popovic, T. Barwicz, E. Ippen, and F. X. Kärtner, “Global design rules for silicon microphotonic waveguides: sensitivity, polarization and resonance tunability,” in Conference on Lasers and Electro-Optics (Optical Society of America, 2006), CTuCC1.

25.

M. A. Popovic, Theory and design of high-index-contrast microphotonic circuits (Massachusetts Institute of Technology, 2008).

26.

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009). [CrossRef]

27.

M. Georgas, J. Leu, B. Moss, S. Chen, and V. Stojanovic, “Addressing link-level design tradeoffs for integrated photonic interconnects,” in Custom Integrated Circuits Conference (IEEE, 2011), 1–8.

28.

P. Dong, W. Qian, H. Liang, R. Shafiiha, X. Wang, D. Feng, G. Li, J. E. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “1x4 reconfigurable demultiplexing filter based on free-standing silicon racetrack resonators,” Opt. Express 18(24), 24504–24509 (2010). [CrossRef] [PubMed]

29.

M. Georgas, J. Orcutt, R. J. Ram, and V. Stojanovic, “A monolithically-integrated optical receiver in standard 45-nm SOI,” in European Solid State Circuits Conference (IEEE, 2011), 407–410.

30.

J. Leu and V. Stojanovic, “Injection-locked clock receiver for monolithic optical link in 45nm SOI,” in Asian Solid State Circuits Conference (IEEE, 2011), 149–152.

31.

Q. Xu, B. Schmidt, S. Pradhan, and M. Lipson, “Micrometre-scale silicon electro-optic modulator,” Nature 435(7040), 325–327 (2005). [CrossRef] [PubMed]

32.

Q. Xu, S. Manipatruni, B. Schmidt, J. Shakya, and M. Lipson, “12.5 Gbit/s carrier-injection-based silicon micro-ring silicon modulators,” Opt. Express 15(2), 430–436 (2007). [CrossRef] [PubMed]

33.

F. Liu, D. Patil, J. Lexau, P. Amberg, M. Dayringer, J. Gainsley, H. F. Moghadam, Z. Xuezhe, J. E. Cunningham, A. V. Krishnamoorthy, E. Alon, and R. Ho, “10 Gbps, 530 fJ/b optical transceiver circuits in 40 nm CMOS,” in Symposium on VLSI Circuits (IEEE, 2011), 290–291.

34.

M. R. Watts, W. A. Zortman, D. C. Trotter, R. W. Young, and A. L. Lentine, “Vertical junction silicon microdisk modulators and switches,” Opt. Express 19(22), 21989–22003 (2011). [CrossRef] [PubMed]

OCIS Codes
(250.3140) Optoelectronics : Integrated optoelectronic circuits
(250.5300) Optoelectronics : Photonic integrated circuits
(250.7360) Optoelectronics : Waveguide modulators

ToC Category:
Optoelectronics

History
Original Manuscript: February 15, 2012
Revised Manuscript: March 29, 2012
Manuscript Accepted: April 2, 2012
Published: May 15, 2012

Citation
Jason S. Orcutt, Benjamin Moss, Chen Sun, Jonathan Leu, Michael Georgas, Jeffrey Shainline, Eugen Zgraggen, Hanqing Li, Jie Sun, Matthew Weaver, Stevan Urošević, Miloš Popović, Rajeev J. Ram, and Vladimir Stojanović, "Open foundry platform for high-performance electronic-photonic integration," Opt. Express 20, 12222-12232 (2012)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-20-11-12222


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  24. M. A. Popovic, T. Barwicz, E. Ippen, and F. X. Kärtner, “Global design rules for silicon microphotonic waveguides: sensitivity, polarization and resonance tunability,” in Conference on Lasers and Electro-Optics (Optical Society of America, 2006), CTuCC1.
  25. M. A. Popovic, Theory and design of high-index-contrast microphotonic circuits (Massachusetts Institute of Technology, 2008).
  26. D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE97(7), 1166–1185 (2009). [CrossRef]
  27. M. Georgas, J. Leu, B. Moss, S. Chen, and V. Stojanovic, “Addressing link-level design tradeoffs for integrated photonic interconnects,” in Custom Integrated Circuits Conference (IEEE, 2011), 1–8.
  28. P. Dong, W. Qian, H. Liang, R. Shafiiha, X. Wang, D. Feng, G. Li, J. E. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “1x4 reconfigurable demultiplexing filter based on free-standing silicon racetrack resonators,” Opt. Express18(24), 24504–24509 (2010). [CrossRef] [PubMed]
  29. M. Georgas, J. Orcutt, R. J. Ram, and V. Stojanovic, “A monolithically-integrated optical receiver in standard 45-nm SOI,” in European Solid State Circuits Conference (IEEE, 2011), 407–410.
  30. J. Leu and V. Stojanovic, “Injection-locked clock receiver for monolithic optical link in 45nm SOI,” in Asian Solid State Circuits Conference (IEEE, 2011), 149–152.
  31. Q. Xu, B. Schmidt, S. Pradhan, and M. Lipson, “Micrometre-scale silicon electro-optic modulator,” Nature435(7040), 325–327 (2005). [CrossRef] [PubMed]
  32. Q. Xu, S. Manipatruni, B. Schmidt, J. Shakya, and M. Lipson, “12.5 Gbit/s carrier-injection-based silicon micro-ring silicon modulators,” Opt. Express15(2), 430–436 (2007). [CrossRef] [PubMed]
  33. F. Liu, D. Patil, J. Lexau, P. Amberg, M. Dayringer, J. Gainsley, H. F. Moghadam, Z. Xuezhe, J. E. Cunningham, A. V. Krishnamoorthy, E. Alon, and R. Ho, “10 Gbps, 530 fJ/b optical transceiver circuits in 40 nm CMOS,” in Symposium on VLSI Circuits (IEEE, 2011), 290–291.
  34. M. R. Watts, W. A. Zortman, D. C. Trotter, R. W. Young, and A. L. Lentine, “Vertical junction silicon microdisk modulators and switches,” Opt. Express19(22), 21989–22003 (2011). [CrossRef] [PubMed]

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