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Optics Express

Optics Express

  • Editor: C. Martijn de Sterke
  • Vol. 20, Iss. 13 — Jun. 18, 2012
  • pp: 13612–13621
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MNOS stack for reliable, low optical loss, Cu based CMOS plasmonic devices

Alexandros Emboras, Adel Najar, Siddharth Nambiar, Philippe Grosse, Emmanuel Augendre, Charles Leroux, Barbara de Salvo, and Roch Espiau de Lamaestre  »View Author Affiliations


Optics Express, Vol. 20, Issue 13, pp. 13612-13621 (2012)
http://dx.doi.org/10.1364/OE.20.013612


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Abstract

We study the electro optical properties of a Metal-Nitride-Oxide-Silicon (MNOS) stack for a use in CMOS compatible plasmonic active devices. We show that the insertion of an ultrathin stoichiometric Si3N4 layer in a MOS stack lead to an increase in the electrical reliability of a copper gate MNOS capacitance from 50 to 95% thanks to a diffusion barrier effect, while preserving the low optical losses brought by the use of copper as the plasmon supporting metal. An experimental investigation is undertaken at a wafer scale using some CMOS standard processes of the LETI foundry. Optical transmission measurments conducted in a MNOS channel waveguide configuration coupled to standard silicon photonics circuitry confirms the very low optical losses (0.39 dB.μm−1), in good agreement with predictions using ellipsometric optical constants of Cu.

© 2012 OSA

1. Introduction

The Metal-Oxide-Semiconductor (MOS) structure is a ubiquitous key building block in the Si-based VLSI electronics industry. Until recently, its lower dimension limit has scaled down according to Moore’s law, leading to an increase in both the power dissipation and the circuit delay of electrical interconnections. Using optical technology could offer a higher bandwidth and reduced power consumption, provided that it can be integrated within a CMOS environment [1

1. R. Zia, J. A. Schuller, A. Chandran, and M. L. Brongersma, “Plasmonics: the next chip-scale technology,” Mater. Today 9, 20–27 (2006). [CrossRef]

]. However, due to the diffraction limit of light at telecommunication wavelengths and the low electro-optical effects of silicon, optical components are generally much larger than their electronic counterparts. This could limit the impact of a chip scale integration of optics. One route to fill the size mismatch is to use metals to support optical modes in optical components. Indeed, surface plasmon (SP) modes, which exist at metal surfaces, allow light confinement below the diffraction limit [2

2. W. L. Barnes, A. Dereux, and T. W. Ebbesen, “Surface plasmon subwavelength optics,” Nature 424, 824–830 (2003). [CrossRef] [PubMed]

].

The MOS structure has attractive plasmonic properties, as the incorporation of the oxide close to the metal interface creates a reduced dimension channel for guiding plasmons [3

3. S. Zhu, T. Y. Liow, G. Q. Lo, and D. L. Kwong, “Silicon-based horizontal nanoplasmonic slot waveguides for on-chip integration,” Opt. Express 19, 8888–8902 (2011). [CrossRef] [PubMed]

], whose electric field is greatly enhanced. Amongst numerous possible plasmonic components, the use of MOS plasmon waveguide (PWG) geometry, where the metal layer is also used as electrodes, has been proposed by several teams to achieve an efficient and compact electro-optical control of optical signal [4

4. J. A. Dionne, K. Diest, L. A. Sweatlock, and H. A. Atwater, “Plasmostor: A metal–oxide–Si field effect plasmonic modulator,” Nano Lett. 9, 897–902 (2009). [CrossRef] [PubMed]

6

6. S. Zhu, G. Q. Lo, and D. L. Kwong, “Electro-absorption modulation in horizontal metal-insulator-silicon-insulator-metal nanoplasmonic slot waveguides,” Appl. Phys. Lett. 99, 151114–151116 (2011). [CrossRef]

]. It is well recognized that plasmon device performance critically depends on the control over the optical losses of the plasmon modes. This is determined by the choice of metal(which is often chosen amongst noble metals), the fabrication procedure [7

7. P. Nagpal, N. C. Lindquist, S.-H. Oh, and D. J. Norris, “Ultrasmooth patterned metals for plasmonics and metamaterials,” Science 325, 594–597 (2009). [CrossRef] [PubMed]

9

9. H. S. Lee, C. Awada, S. Boutami, F. Charra, L. Douillard, and R. E. de Lamaestre, “Loss mechanisms of surface plasmon polaritons propagating on a smooth polycrystalline Cu surface,” Opt. Express 20, 8974–8981 (2012). [CrossRef]

], and the nature of nearby materials. Although active plasmonic devices have been improved from the optical viewpoint, no data have been reported on the issue of their electrical reliability, despite the fact that noble metals are well known contaminants which affect the operation of MOS based devices.

In this article, we validate a plasmonic MNOS (Metal-Nitride-Oxide-Silicon) waveguide from both the low optical loss and electrical reliability point of view, in the perspective of integrated fabrication within a CMOS foundry. The careful choice of materials for the plasmonic metal (Cu) and the interfacial layers is discussed. An electrical reliability issue raised by this metal choice is solved by the insertion of an ultrathin nitride diffusion barrier layer between the gate metal and the oxide. An experimental investigation of this MNOS stack is performed by monitoring both electrical breakdown under voltage stress of that capacitance, and optical transmission experiments through CMOS integrated MNOS PWGs.

2. PWG metal choice

Plasmonic losses are highly dependent on the electric field penetration in the metal, therefore the nature and crystalline quality of the latter are critical technological issues. For this reason, several proposed active and passive plasmonic devices [4

4. J. A. Dionne, K. Diest, L. A. Sweatlock, and H. A. Atwater, “Plasmostor: A metal–oxide–Si field effect plasmonic modulator,” Nano Lett. 9, 897–902 (2009). [CrossRef] [PubMed]

, 10

10. L. Chen, J. Shakya, and M. Lipson, “Subwavelength confinement in an integrated metal slot waveguide on silicon,” Opt. Lett. 31, 2133–2135 (2006). [CrossRef] [PubMed]

12

12. Y. Song, J. Wang, Q. Li, M. Yan, and M. Qiu, “Broadband coupler between silicon waveguide and hybrid plasmonic waveguide,” Opt. Express 18, 13173–13179 (2010). [CrossRef] [PubMed]

] use metals such as Ag and Au. However, these materials are not a good choice for a fabrication on a silicon CMOS platform, as they are well known contaminants of MOS devices. Conversely, metals such as Al and Cu are widely used in CMOS foundries, but have been much less studied for plasmon devices [6

6. S. Zhu, G. Q. Lo, and D. L. Kwong, “Electro-absorption modulation in horizontal metal-insulator-silicon-insulator-metal nanoplasmonic slot waveguides,” Appl. Phys. Lett. 99, 151114–151116 (2011). [CrossRef]

, 9

9. H. S. Lee, C. Awada, S. Boutami, F. Charra, L. Douillard, and R. E. de Lamaestre, “Loss mechanisms of surface plasmon polaritons propagating on a smooth polycrystalline Cu surface,” Opt. Express 20, 8974–8981 (2012). [CrossRef]

, 13

13. C. Delacour, S. Blaize, P. Grosse, J. M. Fedeli, A. Bruyant, R. Salas-Montiel, G. Lerondel, and A. Chelnokov, “Efficient directional coupling between silicon and copper plasmonic nanoslot waveguides: toward metal-oxide-silicon nanophotonics.” Nano Lett. 10, 2922–2926 (2010). [CrossRef] [PubMed]

]. Figure 1 shows the propagation losses of a plasmon propagating at a metal-air interface, as a function of free space wavelength, for both Al and Cu. It was calculated by using the formula αSP=14.3×LSP=2π4.3×λ0ε1+ε, where αSP is the propagation loss (in dB/μm), LSP the propagation length of the plasmon mode, ε the dielectric constant of the metal, and λ0 the free space wavelength. For the calculation, we used the dielectric constant of copper which we measured by ellipsometry [9

9. H. S. Lee, C. Awada, S. Boutami, F. Charra, L. Douillard, and R. E. de Lamaestre, “Loss mechanisms of surface plasmon polaritons propagating on a smooth polycrystalline Cu surface,” Opt. Express 20, 8974–8981 (2012). [CrossRef]

], or the dielectric constant of aluminium given by Palik [14

14. E. D. Palik, Handbook of Optical Constants (Academic, 1985).

]. It has recently been demonstrated [9

9. H. S. Lee, C. Awada, S. Boutami, F. Charra, L. Douillard, and R. E. de Lamaestre, “Loss mechanisms of surface plasmon polaritons propagating on a smooth polycrystalline Cu surface,” Opt. Express 20, 8974–8981 (2012). [CrossRef]

] that the optical losses of plasmon propagating at the surface of Cu layers prepared in CMOS foundries was low and in agreement with the ellispometry results. From this simple comparison, we conclude that copper is the best choice for plasmonic devices in terms of optical losses. It is also technologically relevant, as Al has been progressively replaced by Cu in nowadays electrical interconnects [15

15. R. Rosenberg, D. C. Edelstein, C.-K. Hu, and K. P. Rodbell, “Copper metallization for high performance silicon technology,” Annu. Rev. Mater. Sci. 30, 229–262 (2000). [CrossRef]

]. Cu is therefore the most promising metal for the integration of plasmon devices in a CMOS environment, and will be considered below as a metallization of the MOS waveguide.

Fig. 1 Plasmon propagation losses induced by Cu and Al along a metal/dielectric interface for different wavelengths.

3. Diffusion barrier choice

Table 1. Plasmonic MOS mode losses for different diffusion barriers at a wavelength of 1.55μm.

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4. Cu based MNOS capacitor electrical reliability

In order to validate the use of very thin Si3N4 as a diffusion barrier for copper, we fabricated copper gate MNOS and MOS capacitors on 200 mm silicon wafers on the Leti fabrication line. The silicon wafers are p-doped with boron at 4 × 1018 cm−3 (Fig. 4(a)). A damascene patterning technique [27

27. V. Jousseaume, M. Assous, A. Zenasni, S. Maitrejean, B. Remiat, P. Leduc, H. Trouve, C. Le Cornec, M. Fayolle, A. Roule, F. Ciaramella, D. Bouchu, T. David, A. Roman, D. Scevola, T. Morel, D. Rebiscoul, G. Prokopowicz, M. Jackman, C. Guedj, D. Louis, M. Gallagher, and G. Passemard, “Cu/ULK (k=2.0) integration for 45 nm node and below using an improved hybrid material with conventional BEOL processing and a late porogen removal,” in “Proceedings of the IEEE 2005 International Interconnect Technology Conference,” 60–62 (2005).

] was used in order to fabricate the metal gate electrode of the capacitors. An 800 nm thick thermal oxide was first deposited on the silicon wafers (Fig. 4(b)). A cavity was subsequently drilled into the oxide layer by a lithography step followed by dry and wet etching steps (Fig. 4(c)). Wet etching allows cleaning of the Si interface before the fabrication of the gate dielectric stack. After etching, a 10 nm thermal oxide layer was formed by thermal annealing (Fig. 4(d)). Except for reference purposes, wafers were then submitted to a deposition via LPCVD of a stoichiometric Si3N4 layer on top of the oxide (Fig. 4(e)). A copper layer was then deposited by a combination of the PVD and Electro Chemical Deposition (ECD) and polished by Chemical Mechanical Polishing (CMP) [28

28. R. J. Gutmann, J. M. Steigerwald, L. You, D. T. Price, J. Neirynck, D. J. Duquette, and S. P. Murarka, “Chemical-mechanical polishing of copper with oxide and polymer interlevel dielectrics,” Thin Solid Films 270, 596–600 (1995). [CrossRef]

]. Finally, an Al contact was fabricated on top of copper electrode, followed by thermal stressing at 400 °C (Fig. 4(f)) to simulate the typical thermal budget of a backend process. An investigation of the electrical behavior of such capacitors allows the study of the influence of both the Cu and the silicon nitride on the device performance. C-V measurements were automatically performed using an HP4284 impedance analyser meter at room temperature and a frequency of 100 kHz with an AC voltage of 40 mV in addition to the DC biasing of the device in steps of 0.01 V. Figure 4 shows a typical example of the C-V characteristics of a MOS and a MNOS stack. Both the accumulation and the depletion regimes can be distinguished. The inversion regime is not observed at positive voltages because the voltage sweep frequency is too high to allow the diffusion of minority carriers. These C-V experimental curves were well fitted using an equilibrium capacitance model involving Poisson equation and quantum mechanical corrections [29

29. C. Leroux, F. Allain, A. Toffoli, G. Ghibaudo, and G. Reimbold, “Automatic statistical full quantum analysis of C-V and I-V characteristics for advanced mos gate stacks,” Microelectron. Eng. 84, 2408–2411 (2007). [CrossRef]

], allowing the extraction of the equivalent oxide thickness (EOT) and flat band voltage Vfb (Table 2). Note that the inversion regime is observed in the simulation due to the assumption of equilibrium. The EOT for both gate stacks are in full agreement with the dielectric constant of the insulators used [30

30. J. Robertson, “High dielectric constant gate oxides for metal oxide si transistors,” Rep. Prog. Phys. 69, 327–396 (2006). [CrossRef]

] and measured thicknesses, owning to the quantum corrections of the C-V model. No hysteresis of the C-V curve is observed, indicating that no slow trapping of charge occurs in the silicon nitride and/or in the oxide barrier. However a negative voltage shift of the flat band voltage is observed after the introduction of the nitride layer in the stack, which is commonly attributed to the increased negative fixed charge contained in the silicon nitride layer [31

31. H. Jin and K. J. Weber, “The effect of LPCVD silicon nitride deposition on the Si-SiO2 interface of oxidized silicon wafers,” J. Electrochem. Soc. 154, H5–H8 (2007). [CrossRef]

].

Fig. 2 Fabrication process of MOS capacitors using standard CMOS technology.

Table 2. EOT, Vfb and Cox of given MOS stack layer, extracted by fitting to C-V measurements. Values are averaged out of 10 different devices, for each gate stack.

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Fig. 3 C-V characteristic of MOS capacitor at 100 kHz voltage sweep frequency, for a singe oxide (MOS, black symbol) and an oxide/nitride barrier (MNOS, blue symbol). The corresponding quantum simulation of the curve is also shown for the MOS and MNOS capacitors (black and blue line respectively), follow the model presented in [29].
Fig. 4 (a) Experimental reliability plot (in Weibul scale) of the break down field. (b) SIMS measurement of depth profile of copper intensity for MOS and MNOS multilayer insulator.

In conclusion, a MNOS stack can fulfill the requirement for highly electrically reliable structures, owing to efficient copper diffusion barrier induced by the thin Si3N4. This result is consistent with the demands of CMOS technology.

5. Cu based MNOS PWG integration

This MNOS stack is therefore a reliable platform for CMOS integrated fabrication of PWGs that is compatible with silicon photonics circuitry [35

35. M. Lipson, “Guiding, modulating, and emitting light on silicon-challenges and opportunities,” J. Lightwave Technol. 23, 4222–4238 (2005). [CrossRef]

]. In the following, we butt-coupled a MNOS PWG to standard channel Si waveguides of 220 nm × 500 nm cross section, in a way similar to [36

36. G. Veronis and S. Fan, “Theoretical investigation of compact couplers between dielectric slab waveguides and two-dimensional metal-dielectric-metal plasmonicwaveguides,” Opt. Express 15, 1211–1221 (2007). [CrossRef] [PubMed]

]. Light was coupled in and out of this Si waveguide using gratings [37

37. C. Kopp, E. Augendre, R. Orobtchouk, O. Lemonnier, and J.-M. Fedeli, “Enhanced fiber grating coupler integrated by wafer-to-wafer bonding,” J. Lightwave Technol. 29, 1847–1851 (2011). [CrossRef]

]. Fabrication was undertaken on an 8 inche silicon-on-insulator (SOI) platform. The initial wafer consists of a 220 nm Si layer on a 120 nm buried oxide (BOX) (Fig. 5(a)). Coupling gratings of 950 nm period, 70 nm depth and 50 % duty cycle were first dry etched into the top silicon layer, their dimensions being chosen so that the fundamental TM mode of the Si channel waveguide was efficiently coupled at 1.55 μm operation wavelength. The channel silicon waveguides were fabricated by photolithography and etching down to the silicon substrate (Fig. 5(b)). Planar encapsulation of this layer was performed with a conformal 60 nm thick Si3N4 layer and TEOS oxide followed by CMP step (5(c), (e)). The MNOS PWG was fabricated using damascene technique, meaning a cavity is first drilled in the encapsulation until the Si waveguide surface is reached, after which the silicon thickness of the MNOS stack was adjusted to 170 nm by dry etching. The MNOS stack was fabricated using the same fabrication process as the MNOS capacitor described in section 4. The damascene technique appears particularly well suited for high quality PWG fabrication as (i) the patterning of the metal is achieved thanks to well mastered and standard oxide/nitride etching steps, (ii) it prevents the formation of optically absorbing copper oxide at the interface where plasmon modes are propagating [9

9. H. S. Lee, C. Awada, S. Boutami, F. Charra, L. Douillard, and R. E. de Lamaestre, “Loss mechanisms of surface plasmon polaritons propagating on a smooth polycrystalline Cu surface,” Opt. Express 20, 8974–8981 (2012). [CrossRef]

], and (iii) it uses a high temperature annealing of the metal which favors high material quality and extremely low optical loss SPP propagation. After encapsulation of the MNOS PWG by nitride and oxide deposition, the wafer was transferred onto a 2 μm oxidized Si carrier wafer by direct bonding, and the Si substrate of the initial SOI wafer was removed by mechanical grinding and chemical etching down to the BOX. In using this method, we anticipate the fabrication of a plasmostor [4

4. J. A. Dionne, K. Diest, L. A. Sweatlock, and H. A. Atwater, “Plasmostor: A metal–oxide–Si field effect plasmonic modulator,” Nano Lett. 9, 897–902 (2009). [CrossRef] [PubMed]

] in a vertically integrated channel configuration. The final cross section of the MNOS PWG is shown in (Fig. 5(d), 5(f)).

Fig. 5 (a–d) Fabrication progress of MNOS plasmonic WG, using fully CMOS compatible technology; (e) SEM image of the final Si-WG; (f) SEM image of the final PWG.

6. Cu based MNOS PWG optical transmission

Transmission measurements through the MNOS PWG were performed using a fiber based 1.55 μm laser optical source, whose output was coupled to the TM-polarized mode of the photonic waveguide through grating couplers using monomode fiber. The optical axis of the monomode fiber was fixed at an angle 10° with respect to the surface of the wafer. A multimode fiber was positioned at the output grating and the optical transmission measured through the whole sample using an ANDO AQ2140 optical multimeter. A KARL SUSS automatic wafer probe station was used to switch between samples on the wafer. The data were normalized with the optical transmission of a reference 220 nm × 500 nm silicon waveguide (SiWG) placed close to every group of 34 PWG samples. Wafer scale fabrication allows a large number of devices to be tested. Figure 6(c) displays the normalized transmission of about 1000 PWGs whose silicon thickness is 170 nm and the length LPWG is varied between 2 and 7 μm. For each device length LPWG, the transmitted power is measured for 18 identical PWGs taken at various positions on the wafer.

Fig. 6 (a) Cross section in the propagation direction indicating the main components of the hybrid plasmonic WG. (b) The E and H field intensity of the fundamental plasmonic mode suported in Si WG and plasmonic WG taken from 3D mode analysis using FDTD. (c) Normalized transmission data as a function of the LPWG. The experimental fit (red line) and the raw transmission data of 1000 devices (black symbols) are shown.

7. Conclusion

We proposed a MNOS stack for applications in electro-optical plasmonic devices, so that a very low optical losses and reliable operation is achieved. This objective is met thanks to a careful choice of materials, copper as a plasmon supporting metal and stoechiometric silicon nitride as a ultrathin diffusion barrier to the latter, and the use of fully CMOS compatible processes to integrate the MNOS plasmonic waveguide within silicon photonics circuitry. Final reliability is above 95% for a 3 nm thick Si3N4 layer and optical losses as low as 0.4 dB.μm−1 for a 13 nm thick insulator barrier, in agreement with the Cu ellispometric data. These results open the way towards the high performance and low cost fabrication of plasmonic active devices within CMOS foundries.

Acknowledgments

This work has been supported by CEA internal Programme Transverse Nanoscience, the French National Agency (ANR) through LETI Carnot Funding. We acknowledge the Leti CMOS platform team for assistance in sample fabrication, David Fowler for his careful reading of the manuscript, K. Gilbert for technical contribution regarding the experiment and M. Veillerot and J.P. Barnes for assistance to SIMS measurement.

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OCIS Codes
(230.7370) Optical devices : Waveguides
(240.6680) Optics at surfaces : Surface plasmons
(250.5403) Optoelectronics : Plasmonics

ToC Category:
Optics at Surfaces

History
Original Manuscript: February 24, 2012
Manuscript Accepted: April 2, 2012
Published: June 4, 2012

Citation
Alexandros Emboras, Adel Najar, Siddharth Nambiar, Philippe Grosse, Emmanuel Augendre, Charles Leroux, Barbara de Salvo, and Roch Espiau de Lamaestre, "MNOS stack for reliable, low optical loss, Cu based CMOS plasmonic devices," Opt. Express 20, 13612-13621 (2012)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-20-13-13612


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