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Optics Express

  • Editor: C. Martijn de Sterke
  • Vol. 20, Iss. 16 — Jul. 30, 2012
  • pp: 18145–18155

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High-speed receiver based on waveguide germanium photodetector wire-bonded to 90nm SOI CMOS amplifier

Huapu Pan, Solomon Assefa, William M. J. Green, Daniel M. Kuchta, Clint L. Schow, Alexander V. Rylyakov, Benjamin G. Lee, Christian W. Baks, Steven M. Shank, and Yurii A. Vlasov  »View Author Affiliations


Optics Express, Vol. 20, Issue 16, pp. 18145-18155 (2012)
http://dx.doi.org/10.1364/OE.20.018145


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Abstract

The performance of a receiver based on a CMOS amplifier circuit designed with 90nm ground rules wire-bonded to a waveguide germanium photodetector is characterized at data rates up to 40Gbps. Both chips were fabricated through the IBM Silicon CMOS Integrated Nanophotonics process on specialty photonics-enabled SOI wafers. At the data rate of 28Gbps which is relevant to the new generation of optical interconnects, a sensitivity of −7.3dBm average optical power is demonstrated with 3.4pJ/bit power-efficiency and 0.6UI horizontal eye opening at a bit-error-rate of 10−12. The receiver operates error-free (bit-error-rate < 10−12) up to 40Gbps with optimized power supply settings demonstrating an energy efficiency of 1.4pJ/bit and 4pJ/bit at data rates of 32Gbps and 40Gbps, respectively, with an average optical power of −0.8dBm.

© 2012 OSA

1. Introduction

Monolithic integration of optical components such as modulators, germanium photodetectors, and WDM filters with CMOS analog and mixed signal (AMS) circuits is viewed as a possible solution for cost-effective and low-power optical interconnects that can empower various market solutions spanning from Ethernet links for 2–5 km reach in the new generation datacenters to optical backplanes in servers and routers for a reach as short as just a meter [1

Y. A. Vlasov, “Silicon CMOS-Integrated Nano-Photonics for Computer and Data Communications Beyond 100G,” IEEE Commun. Mag. 50, S67–S72 (2012).

]. However, the performance to date of CMOS-based AMS circuits, and especially TIA/LA amplifiers, has been bandwidth-limited to data rates of no more than 30Gbps even in the advanced CMOS nodes [2

C. L. Schow, “Power-Efficient Transceivers for High-Bandwidth, Short-Reach Interconnects,” Optical Fiber Communication Conference (OFC), OTh1E.4 (2012).

–11

C. L. Schow, A. V. Rylyakov, C. Baks, F. E. Doany, and J. A. Kash, “A 25 Gb/s, 6.5 pJ/bit, 90-nm CMOS-driven multimode optical link,” IEEE Photon. Technol. Lett. 24(10), 824–826 (2012). [CrossRef]

]. Even though utilization of silicon germanium (SiGe) bipolar AMS circuits in a front-end amplifiers was shown to perform well at bit rates as high as 40Gbps [12

L. Chen, C. R. Doerr, L. Buhl, Y. Baeyens, and R. A. Aroca, “Monolithically integrated 40-wavelength demultiplexer and photodetector array on silicon,” IEEE Photon. Technol. Lett. 23(13), 869–871 (2011). [CrossRef]

,13

A. V. Rylyakov, C. L. Schow, J. Proesel, D. M. Kuchta, C. Baks, N. Y. Li, C. Xie, and K. Jackson, “A 40-Gb/s, 850-nm, VCSEL-Based Full Optical Link,” Optical Fiber Communication Conference (OFC), OTh1E.1 (2012).

], monolithic integration of photonic circuits into these technologies is problematic because to date all of the SiGe bipolar AMS circuit are fabricated on bulk Si substrate. Recently several receiver circuits in 90nm and 45nm CMOS nodes have been demonstrated with data rates up to 40Gbps [14

C. F. Liao and S. Liu, “40 Gb/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90 nm CMOS,” IEEE J. Solid-state Circuits 43(3), 642–655 (2008). [CrossRef]

,15

J. Kim and J. F. Buckwalter, “A 40-Gb/s optical transceiver front-end in 45 nm SOI CMOS,” IEEE J. Solid-state Circuits 47(3), 615–626 (2012). [CrossRef]

]. However, these receiver circuits have only been tested electrically. Morever, no optical receiver using CMOS-based AMS circuits, especially one using a germanium (Ge) waveguide photodetector (PD) has been demonstrated at 40Gbps. Here we present a detailed performance study of an optical receiver consisting of a CMOS AMS amplifier circuit designed with 90nm ground rules that is wire-bonded to a waveguide Ge PD Both chips were fabricated with the IBM Silicon CMOS Integrated Nanophotonics (SCIN) process [16

S. Assefa, W. M. Green, A. V. Rylyakov, C. L. Schow, F. Horst, and Y. A. Vlasov, “CMOS Integrated Silicon Nanophotonics: Enabling Technology for Exascale Computational Systems,” Optical Fiber Communication Conference (OFC), OMM6 (2011).

,17

W. M. Green, A. V. Rylyakov, C. L. Schow, F. Horst, and Y. A. Vlasov, “CMOS integrated Silicon Nanophotonics: Enabling Technology for Exascale Computational Systems,” Proc. SEMICON, Chiba, Japan, Dec. 1–3, 2010, available: http://www.research.ibm.com/photonics.

] on a specialty photonics-enabled SOI wafer. Performance parameters such as jitter, sensitivity and energy efficiency have been characterized up to 40Gbps.

2. Hybrid-integrated receiver and the measurement setup

Figure 1(a) shows a photograph of the hybrid-integrated photodetector and amplifier. The waveguide-integrated metal-semiconductor-metal Ge PD [8

S. Assefa, F. Xia, S. W. Bedell, Y. Zhang, T. Topuria, P. M. Rice, and Y. A. Vlasov, “CMOS-integrated high-speed MSM germanium waveguide photodetector,” Opt. Express 18(5), 4986–4999 (2010). [CrossRef] [PubMed]

] was fabricated with the IBM SCIN process [16

S. Assefa, W. M. Green, A. V. Rylyakov, C. L. Schow, F. Horst, and Y. A. Vlasov, “CMOS Integrated Silicon Nanophotonics: Enabling Technology for Exascale Computational Systems,” Optical Fiber Communication Conference (OFC), OMM6 (2011).

,17

W. M. Green, A. V. Rylyakov, C. L. Schow, F. Horst, and Y. A. Vlasov, “CMOS integrated Silicon Nanophotonics: Enabling Technology for Exascale Computational Systems,” Proc. SEMICON, Chiba, Japan, Dec. 1–3, 2010, available: http://www.research.ibm.com/photonics.

]. The photodetector has an internal responsivity of 0.5A/W at 1V bias for the wavelength of 1310nm and a relatively large dark current of 120µA. Comparing with Ref [8

S. Assefa, F. Xia, S. W. Bedell, Y. Zhang, T. Topuria, P. M. Rice, and Y. A. Vlasov, “CMOS-integrated high-speed MSM germanium waveguide photodetector,” Opt. Express 18(5), 4986–4999 (2010). [CrossRef] [PubMed]

], the Ge PD is re-designed for improved responsivity at both 1310nm and 1550nm achieved by changing the width and thickness of the Si and Ge layers. The photodetector was wire-bonded to the CMOS amplifier schematically shown in Fig. 1(b). The CMOS amplifier was designed with 90nm design rules and fabricated using the IBM SCIN process on specialty SOI wafers having 200nm thick silicon device layer on top of 2µm buried oxide (BOX) thickness. The AMS receiver circuit consists of a trans-impedance amplifier (TIA) with 150Ω transimpedance gain followed by a six-stage limiting amplifier (LA) and a current-mode logic output stage (OS) buffer. Four separate power supplies (VPD_bias, VDD_TIA, VDD_LA and VDD_OS) are individually tuned for best performance. The power consumed by the receiver is measured by the sum of the voltage-current product of the four power supplies. The photodetector was DC biased through two 2kΩ resistors. The photodetector output current was AC coupled to the differential TIA.

Fig. 1 (a) Right-hand side: Photograph showing the waveguide-integrated Ge PD chip wire-bonded to the CMOS amplifier chip; Left-hand side: magnified image of the waveguide-integrated Ge PD with interdigitated contacts. (b) Schematic of the CMOS receiver amplifer consisting of a trans-impedance amplifier (TIA) followed by a six-stage limiting amplifier (LA) and a current-mode logic output stage (OS) buffer. Four separate power supplies are individually tuned for best performance. Receiver power consumption is measured from the sum of the voltage-current product of the four power supplies. (c) Schematic of the measurement setup. The LiNbO3 modulator was driven by a pseudo-random bit sequence of length 27–1 (PRBS7). Optical eye at the output of the modulator and the electrical eye at the receiver output measured at 40Gbps are shown with an average optical power of −0.8dBm.

The measurement setup used to characterize the receiver is shown in Fig. 1(c). TE-polarized light from a 1310nm DFB laser was modulated with a commercial Lithium Niobate (LiNbO3) modulator and launched into the SiON-based coupler [19

S. Assefa, C. Jahnes, and Y. Vlasov, “CMOS compatible integrated dielectric optical waveguide coupler and fabrication,” US Patent 2009/0324162 A1, filed June 2008.

] of the photodetector chip using a lensed fiber. The LiNbO3 modulator was driven by a pseudo-random bit sequence (PRBS) of length 27–1 from a SHF BPG 44E pattern generator amplified by a high-speed SHF 810 RF amplifier in all of the following measurements described in this paper. 27–1 PRBS input is used instead of 231–1 PRBS input because the receiver circuit is designed to AC couple the photocurrent and thus has a low frequency cutoff at 30MHz. This design is relevant for applications with 8b/10b and similar coding schemes. It is sufficient to pass a short PRBS of length 27–1 at data rates above 10Gbps, but not enough to pass longer PRBS of length 231–1. One of the differential electrical outputs of the receiver was monitored by a high-speed Tektronix CSA8200 digital sampling oscilloscope, while the other was connected to a SHF EA 44 bit-error-rate tester operating up to 40Gbps. A typical transmitter eye diagram and a receiver eye diagram at 40Gbps are also shown in Fig. 1(c), as measured with an average optical power of −0.8dBm at the photodetector input. For improved measurement accuracy, the bathtub curves at 28Gbps and sensitivity curves below 28Gbps are measured by replacing the SHF BPG 44E pattern generator and the SHF EA 44 bit-error-rate tester with the Anritsu MP1800A Signal Quality Analyzer consisting of a 28Gbps pattern generator and error detector. Otherwise all the measurements presented in this paper are carried out with the measurement setup described above.

The average optical power Pavg reported in all the measurement data refers to half of the optical modulation amplitude (OMA), and thus is different from the optical power Pmeas measured with an optical power meter in the case that the extinction ratio ER = P1/P0 of the modulator is not infinite. These quantities are related by the following equation Pmeas = Pavg[(ER + 1)/(ER-1)], as depicted in the transmitter eye schematic in Fig. 1(c). In the following sections, the average optical power is computed by dividing the measured optical power with a correction factor [(ER + 1)/(ER-1)] to account for the non-ideal extinction ratio of the LiNbO3 modulator. On a decibel scale, this correction factor is calculated by 10log[(ER + 1)/(ER-1)]. The ER for the LiNbO3 modulator in this setup is 18, with a corresponding correction factor of 0.5dB.

The average optical power arriving at the photodetector was calculated from the optical power measured at the fiber output by subtracting the fiber-to-chip coupling loss and correcting for non-ideal extinction ratio of the modulator. To calculate the optical coupling loss, first the fiber-to-fiber insertion loss to a chip containing a 4mm long straight silicon reference waveguide without a photodetector is measured. The total optical insertion loss is 14dB for the same sample under test that comprise both coupling loss at two fiber-to-waveguide interfaces and propagation loss in the reference waveguide. Since the photodetector is located at the middle of the Ge PD chip, half of this loss, 7dB, is therefore the receiver insertion loss, of which approximately 6dB is due to the fiber-to-chip coupling loss and 1dB is due to waveguide propagation loss.

To confirm the sensitivity measurements, an alternative method to estimate the average optical power at the PD was also used that is based on direct measurements of the photocurrent at the output of the PD in the wire-bonded package. When VPD_bias is 2.5V, the dark current of the PD is measured as 280µA. Taking into consideration the voltage drop induced by the two 2kΩ biasing resistors (see schematics of Fig. 1(b)), the voltage drop across the photodetector can be calculated by VPD = VPD_bias - 4kΩ × Idark = 1.4V. In this bias condition, the net photocurrent of the photodetector at the bit-error-ratio (BER) of 10−12 was measured by subtracting the dark current from the measured total current at the corresponding bias voltage when the photodetector is illuminated. Then, the average optical power was calculated by dividing the measured photocurrent with the responsivity of the photodetector, 0.5A/W. The resulting sensitivity measured with these two alternative methods shows very similar results within ± 0.7 dB error. In this paper, all the sensitivity data is reported using the first method of calculating the average optical power arriving at the photodetector.

3. Receiver performance up to 28Gbps

Communication standards such as IEEE 100G Ethernet require 25Gbps line rate, while OIF 28G-VSR chip-to-chip interconnects specifies 28Gbps line rate. In this section, the performance of the receiver is characterized in detail up to 28Gbps targeting these applications. Eye diagrams of the receiver at different data rates are measured with an average optical power of −5.5dBm at the PD input and the results are shown in Fig. 2 . At 28Gbps the eye diagram shows a total peak-to-peak jitter (TJpp) of 6.7ps, a 10%-90% rise/fall time of 15.7ps and a single-ended amplitude of 256mV peak-to-peak. At 30Gbps the eye diagram of the receiver shows no signs of degradation, indicating that the receiver can operate well beyond the OIF 28G-VSR line rate specification.

Fig. 2 Electrical eye diagrams at the receiver output measured at various data rates with 97.2mW power drawn from all four power supplies on the receiver and an average input optical power of −5.5dBm.

Figure 3(a) shows the BER curves for data rates up to 28Gbps measured with the constant power consumption at the receiver of 97.2mW. This receiver bias condition is chosen to achieve BER<10−12 at 28Gbps with the minimum power consumption. The resulting sensitivities are −7.3, −8.4, −9.9 and −11.9 dBm average optical power at a BER of 10−12 for data rates of 28Gbps, 25Gbps, 20Gbps and 10Gbps, respectively. Thus an energy efficiency of 3.4pJ/bit is achieved at 28Gbps with this optimized receiver bias conditions.

Fig. 3 (a) BER curves of the receiver measured using PRBS7 at various data rates. Power settings correspond to total receiver power consumption of 97.2mW ; (b) 28Gbps bathtub curve measured at average optical power of 1dB and 5dB higher than the 10−12 BER sensitivity for Ge PD Rx and 5dB higher than the 10−12 BER sensitivity for a commercial InP Rx with the same power supply settings as the BER curve measurement.

To further characterize the Ge PD receiver, the bathtub curves at 28Gbps were measured as shown in Fig. 3(b). Two measurements with average optical powers of −6.3dBm and −2.3dBm were performed, which are 1dB and 5dB higher than the 10−12 BER sensitivity, respectively. The corresponding horizontal eye openings are approximately 0.5UI and 0.6UI at the BER of 10−12. For comparison the bathtub curve of a reference 40Gbps InP-based commercial receiver is measured using the same setup and PRBS pattern with an average optical power 5dB higher than its 10−12 BER sensitivity. The commercial 40Gbps receiver shows a horizontal eye opening of 0.65UI at the BER of 10−12, which is only slightly higher than the Ge PD receiver.

For the measurements shown in Fig. 4(a) , the average optical power is kept constant at −7.3dBm, i.e., at the PD which is the minimum optical power required to achieve a BER of 10−12 at 28Gbps. Energy efficiency is measured at each data rate as a sum of the voltage-current product of the four power supplies divided by the data rate. During measurements the voltage biases on the TIA, LA and OS stages of the receiver are tuned for each data rate to achieve the 10−12 BER while minimizing total power consumption. While tuning the supply voltages the output differential peak-to-peak voltage swing from the OS stage was maintained higher than 100mV, which is sufficient for most optical communication system applications. The best energy efficiency of 1.9pJ/bit was obtained at 22Gbps. The energy efficiency degrades with decreasing data rate below 22Gbps because the power to maintain 100mV peak-to-peak is constant while data rate is decreasing. Moderately higher power consumption is needed to operate the receiver circuit faster than 22Gbps because higher bias on the receiver circuit is required to boost the circuit bandwidth.

Fig. 4 (a). Energy efficiency measured with an average optical power of −7.3dBm at various data rates. Power settings are optimized for each data rate measured to minimize the power consumptions while maintaining BER<10−12 and 100mV peak-to-peak single-ended output (b). Receiver sensitivity taken at 10−12 BER versus energy efficiency measured at 25 and 28Gbps

Figure 4(b) shows measurements of the sensitivity penalty resulting from reduction of the receiver power consumption at data rates of 25Gbps and 28Gbps. At a given data rate, the sensitivity at BER of 10−12 is measured while gradually decreasing the voltage on VDD_LA power supply. For the data rate of 25Gbps, a significant 33% improvement of the energy efficiency from 4.9pJ/bit to 3.3pJ/bit results in a relatively small sensitivity penalty of less than 0.2dB. Further improvement of the energy efficiency results in a significant sensitivity penalty approaching 2dB. At the data rate of 28Gbps, a 0.2dB penalty is observed when the energy efficiency is improved by 29% from 4.5pJ/bit to 3.2pJ/bit. At power supply settings corresponding to an energy efficiency of 3.4pJ/bit, the sensitivity is measured as −7.3dBm.

4. Receiver performance at data rates up to 38Gbps

Figure 5(a) shows the eye diagrams of the receiver measured at extended data rates up to 38Gbps with an average optical power of −0.8dBm, for which the power consumption of the receiver is increased to 119.8mW. Similar to the eye diagrams in Fig. 2, the eye diagrams in Fig. 5(a) are measured with 400 acquisitions.

Fig. 5 (a) Eye diagrams at various data rates measured at an average optical power of −0.8dBm; Power settings corresponds to a total receiver power consumption of 119.8mW (b) Receiver BER curves at various data rates with receiver power supply settings equivalent to those in (a).

Figure 5(b) shows the measured BER curves and the corresponding sensitivities are −0.8, −2.8, −5 and −6.5dBm average optical power at a BER of 10−12 for data rates of 38Gbps, 36Gbps, 32Gbps, and 28Gbps respectively. The sensitivity at 28Gbps is slightly degraded in comparison with the sensitivity shown in Fig. 3(a) likely because VPD has increased from 1.4V to 2.1V, and thus the dark current of the photodetector has increased from 280µA to 350µA, which results in larger shot noise.

Figure 6(a) shows bathtub curves measured at 28Gbps and 36Gbps. Both bathtub curves were obtained with an average optical power 1dB higher than the 10−12 BER sensitivity. The horizontal eye opening is approximately 0.5UI and 0.45UI at the BER of 10−12 for data rates of 28Gbps and 36Gbps, respectively.

Fig. 6 (a) Bathtub curves at 28Gbps and 36Gbps measured with an average optical power 1dB higher than the 10−12 BER sensitivity. Power settings correspond to a total receiver power consumption of 119.8mW. (b) Energy efficiency versus data rates with an average optical power of −0.8dBm. At each data rate tested, receiver supply voltages are optimized for each data rate measured to minimize the power consumptions while maintaining BER<10−12 and 100mV peak-to-peak single-ended output

Figure 6(b) shows energy efficiency measurement with the average optical power fixed at −0.8dBm, which is the minimum optical power required to maintain the BER of 10−12 at 38Gbps. Similar to the previous energy efficiency measurement as in Fig. 4(a), the output differential peak-to-peak voltage swing from the OS stage was maintained higher than 100mV while tuning the supply voltages on the receiver circuit to minimize total power consumption. As shown in Fig. 6(b), the best energy efficiency of 1.4pJ/bit was obtained at 32Gbps.

5. Receiver performance at 40Gbps

To achieve a BER of 10−12 at 40Gbps, the bias on the receiver circuit was further optimized which increased the total power consumption to 158.4mW, corresponding to an energy efficiency of 4.0pJ/bit. With these bias settings, error free operation at 40Gbps is achieved with a sensitivity of −0.8dBm average optical power as shown in Fig. 7(a) . The last three data points in Fig. 7(a) were obtained by bypassing the variable optical attenuator so as to reach sufficient optical power, which might explain the change in the slope of the BER curve. The bathtub curve shown in Fig. 7(b) is measured at an average optical power only 0.3dB higher than the 10−12 BER sensitivity. Note that the maximum available optical power in the experimental setup was −0.5dBm. Due to the same optical power limitation the bathtub curve shown in Fig. 7(b) is measured only down to the BER of 10−10 where a horizontal eye opening of 0.4UI is obtained.

Fig. 7 (a) BER curve of the receiver measured at 40Gbps with power supply settings corresponding to total receiver power consumption of 158.4mW. (b). Bathtub curve measured at an average optical power 0.3dB higher than the 10−12 BER sensitivity with the same power supply settings as the BER curve measurement in (a)

In order to further investigate the mechanisms which improve the BER of the receiver when average optical power is increased, the eye diagrams of the receiver at 40Gbps are measured at two different average optical power levels of −4.5dBm and −0.8dBm, which correspond to the BER of 5 × 10−5 and 1 × 10−12, respectively, as shown in Fig. 8(a) and Fig. 8(b). The eye amplitude is the same for both optical power levels indicating that the LA of the receiver is fully limiting. Thus vertical eye closure is not the dominating factor defining the BER curves in Fig. 7(a). As the average optical power is increased from −4.5dBm to −0.8dBm, which corresponds to the increase of the peak-to-peak photocurrent from 355µApp to 832µApp, the 10%-90% fall time, as measured from the eye diagrams in Fig. 8, is decreased from 14.5ps to 11.5ps. This indicates that the receiver is becoming faster at higher input photocurrent levels.

Fig. 8 Eye diagrams of the receiver at 40Gbps with an average optical power of (a) −4.5dBm and (b) −0.8dBm. Power supply settings corresponds to a total receiver power consumption of 158.4mW

This observation is confirmed by measurements of the TJpp dependence on the input optical power level, using the eye diagrams in Fig. 8. The TJpp measured at −4.5dBm average optical power from Fig. 8(a) is very large, reaching 12.3ps. With average optical power increased to −0.8dBm, the TJpp is reduced to 7.8ps as shown in Fig. 8(b). This indicates that the bandwidth of both the TIA and the early stages of LA are becoming the limiting factors of the receiver performance since the inter-symbol interference of the TIA and early stages of LA translates into jitter at the output of the LA.

6. Discussion

As it is concluded in the analysis of the 40Gbps data, the dependence of the receiver circuit bandwidth upon input peak-to-peak photocurrent is one of the major sources of sensitivity degradation. Since the PD bandwidth is very high (40GHz at 1V as mentioned in Section 2), the receiver sensitivity degradation related to PD bandwidth is almost negligible. As shown in Fig. 3(a), degradation of the 10−12 BER sensitivity from −11.9dBm to −7.3dBm, corresponding to peak-to-peak photocurrents of 65 µApp and 186 µApp, respectively, is observed when the data rate increases from 10Gbps to 28Gbps. Considering the 150Ω transimpedance gain of the TIA, the peak-to-peak input electrical signal swing to the LA stage increased correspondingly from 10mVpp to 28mVpp. As the data rate further increased to 38Gbps, as shown in Fig. 5(b), the 10−12 BER sensitivity degraded to −0.8dBm. The corresponding peak-to-peak photocurrent is 831 µApp and the peak-to-peak input electrical signal swing to the LA stage is 125mVpp. Larger input photocurrent to the TIA and thus larger input electrical signal swing to the LA is required for the receiver to achieve the 10−12 BER at higher data rate, because the larger input electrical signal swing can reduce the switching time of the CMOS transistors and thus increase the bandwidth of the receiver circuit as a whole.

This trade-off between the receiver bandwidth and the receiver sensitivity is intrinsic to the design of the analog CMOS circuit. Similar circuit performance has been reported by recent publications on 40Gbps TIA in 90nm bulk technology [14

C. F. Liao and S. Liu, “40 Gb/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90 nm CMOS,” IEEE J. Solid-state Circuits 43(3), 642–655 (2008). [CrossRef]

] and 45nm SOI technology [15

J. Kim and J. F. Buckwalter, “A 40-Gb/s optical transceiver front-end in 45 nm SOI CMOS,” IEEE J. Solid-state Circuits 47(3), 615–626 (2012). [CrossRef]

], although both reports used longer PRBS pattern of length 231-1. Even in advanced 45nm SOI technology, to achieve 40Gbps performance, very high input photocurrent levels close to 1mApp are required [15

J. Kim and J. F. Buckwalter, “A 40-Gb/s optical transceiver front-end in 45 nm SOI CMOS,” IEEE J. Solid-state Circuits 47(3), 615–626 (2012). [CrossRef]

]. Since no sensitivity number is reported in Ref [15

J. Kim and J. F. Buckwalter, “A 40-Gb/s optical transceiver front-end in 45 nm SOI CMOS,” IEEE J. Solid-state Circuits 47(3), 615–626 (2012). [CrossRef]

], it is difficult to make a proper performance comparison. In 90nm bulk technology, the TIA reported in [14

C. F. Liao and S. Liu, “40 Gb/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90 nm CMOS,” IEEE J. Solid-state Circuits 43(3), 642–655 (2008). [CrossRef]

] demonstrated sensitivity of 430µApp at the BER of 10−9, a power consumption of 75mW and the TJpp of 10.9ps, which are comparable to the performance of the Ge PD receiver demonstrated in this paper.

7. Conclusion

Error-free operation (BER<10−12) at data rates up to 40Gbps has been demonstrated for a receiver based on a CMOS amplifier circuit designed with 90nm ground rules wire-bonded to a waveguide germanium photodetector. Both chips were fabricated with the IBM SCIN process on specialty photonics-enabled SOI wafers. At the data rate of 28Gbps which is relevant to the new generation of optical interconnects, a sensitivity of −7.3dBm average optical power is demonstrated with a 3.4pJ/bit power-efficiency and a 0.6UI horizontal eye opening at the BER of 10−12. With optimized power supply settings, the receiver operates error-free up to 40Gbps demonstrating an energy efficiency of 1.4pJ/bit and 4pJ/bit at data rates of 32Gbps and 40Gbps, respectively, with an average optical power of −0.8dBm. The measurement conditions and results are summarized in Table 1 .

Table 1  Summarized measurement conditions and results for various experiments
ExperimentSensitivity at 10−12 BERAverage optical power used (dBm)Total electrical power consumption (mW)Energy efficiency (pJ/bit)
Figure 4 (b) at 28Gbps
−7.3
−7.3
95.2
3.4
Figure 6(b) at 32 Gbps
−5
−0.8
44.8
1.4
Figure 7(a) at 40Gbps−0.8−0.8158.44.0

The results indicate that integrated CMOS receivers are promising for next generation power-efficient optical interconnects such as 100Gbps Ethernet, Fiber Channel, Infiniband, etc. In order to meet the strict requirements of these standards, further improvement of sensitivity is required. In our current receiver design, a 3dB sensitivity improvement can be expected from an increase of responsivity to 1A/W, and more than 1dB improvement can be expected from the reduction of dark current to below 10µA.

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T. Takemoto, F. Yuki, H. Yamashita, S. Tsuji, Y. Lee, K. Adachi, K. Shinoda, Y. Matsuoka, K. Kogo, S. Nishimura, M. Nido, M. Namiwaka, T. Kaneko, T. Sugimoto, and K. Kurata, “100-Gbps CMOS Transceiver for Multilane Optical Backplane System with 1.3-cm2 Footprint, ” 37th European Conference and Exposition on Optical Communications (ECOC), Th.12.B.5. (2011).

7.

A. Narasimha, B. Analui, Y. Liang, T. J. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. G. M. P. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A fully integrated 4 × 10-Gb/s DWDM optoelectronic transceiver implemented in a standard 0.13 µm CMOS SOI technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007). [CrossRef]

8.

S. Assefa, F. Xia, S. W. Bedell, Y. Zhang, T. Topuria, P. M. Rice, and Y. A. Vlasov, “CMOS-integrated high-speed MSM germanium waveguide photodetector,” Opt. Express 18(5), 4986–4999 (2010). [CrossRef] [PubMed]

9.

B. G. Lee, S. Assefa, C. Schow, W. M. Green, A. Rylyakov, R. A. John, J. A. Kash, and Y. A. Vlasov, “Hybrid-Integrated Germanium Photodetector and CMOS Receiver Operating at 15 Gb/s,” Conference on Lasers and Electro-Optics (CLEO), CFB4 (2011).

10.

Q. Fang, Y. T. Phang, C. W. Tan, T. Y. Liow, M. B. Yu, G. Q. Lo, and D. L. Kwong, “Multi-channel silicon photonic receiver based on ring-resonators,” Opt. Express 18(13), 13510–13515 (2010). [CrossRef] [PubMed]

11.

C. L. Schow, A. V. Rylyakov, C. Baks, F. E. Doany, and J. A. Kash, “A 25 Gb/s, 6.5 pJ/bit, 90-nm CMOS-driven multimode optical link,” IEEE Photon. Technol. Lett. 24(10), 824–826 (2012). [CrossRef]

12.

L. Chen, C. R. Doerr, L. Buhl, Y. Baeyens, and R. A. Aroca, “Monolithically integrated 40-wavelength demultiplexer and photodetector array on silicon,” IEEE Photon. Technol. Lett. 23(13), 869–871 (2011). [CrossRef]

13.

A. V. Rylyakov, C. L. Schow, J. Proesel, D. M. Kuchta, C. Baks, N. Y. Li, C. Xie, and K. Jackson, “A 40-Gb/s, 850-nm, VCSEL-Based Full Optical Link,” Optical Fiber Communication Conference (OFC), OTh1E.1 (2012).

14.

C. F. Liao and S. Liu, “40 Gb/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90 nm CMOS,” IEEE J. Solid-state Circuits 43(3), 642–655 (2008). [CrossRef]

15.

J. Kim and J. F. Buckwalter, “A 40-Gb/s optical transceiver front-end in 45 nm SOI CMOS,” IEEE J. Solid-state Circuits 47(3), 615–626 (2012). [CrossRef]

16.

S. Assefa, W. M. Green, A. V. Rylyakov, C. L. Schow, F. Horst, and Y. A. Vlasov, “CMOS Integrated Silicon Nanophotonics: Enabling Technology for Exascale Computational Systems,” Optical Fiber Communication Conference (OFC), OMM6 (2011).

17.

W. M. Green, A. V. Rylyakov, C. L. Schow, F. Horst, and Y. A. Vlasov, “CMOS integrated Silicon Nanophotonics: Enabling Technology for Exascale Computational Systems,” Proc. SEMICON, Chiba, Japan, Dec. 1–3, 2010, available: http://www.research.ibm.com/photonics.

18.

S. Assefa, F. Xia, S. W. Bedell, Y. Zhang, T. Topuria, P. M. Rice, and Y. A. Vlasov, “CMOS-Integrated 40GHz Germanium Waveguide Photodetector for On-chip Optical Interconnects,” Optical Fiber Communication Conference (OFC), OMR4 (2009).

19.

S. Assefa, C. Jahnes, and Y. Vlasov, “CMOS compatible integrated dielectric optical waveguide coupler and fabrication,” US Patent 2009/0324162 A1, filed June 2008.

OCIS Codes
(040.5160) Detectors : Photodetectors
(130.0250) Integrated optics : Optoelectronics
(200.4650) Optics in computing : Optical interconnects

ToC Category:
Detectors

History
Original Manuscript: May 30, 2012
Revised Manuscript: July 13, 2012
Manuscript Accepted: July 16, 2012
Published: July 23, 2012

Citation
Huapu Pan, Solomon Assefa, William M. J. Green, Daniel M. Kuchta, Clint L. Schow, Alexander V. Rylyakov, Benjamin G. Lee, Christian W. Baks, Steven M. Shank, and Yurii A. Vlasov, "High-speed receiver based on waveguide germanium photodetector wire-bonded to 90nm SOI CMOS amplifier," Opt. Express 20, 18145-18155 (2012)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-20-16-18145


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References

  1. Y. A. Vlasov, “Silicon CMOS-Integrated Nano-Photonics for Computer and Data Communications Beyond 100G,” IEEE Commun. Mag.50, S67–S72 (2012).
  2. C. L. Schow, “Power-Efficient Transceivers for High-Bandwidth, Short-Reach Interconnects,” Optical Fiber Communication Conference (OFC), OTh1E.4 (2012).
  3. X. Zheng, D. Patil, J. Lexau, F. Liu, G. Li, H. Thacker, Y. Luo, I. Shubin, J. Li, J. Yao, P. Dong, D. Feng, M. Asghari, T. Pinguet, A. Mekis, P. Amberg, M. Dayringer, J. Gainsley, H. F. Moghadam, E. Alon, K. Raj, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “Ultra-efficient 10 Gb/s hybrid integrated silicon photonic transmitter and receiver,” Opt. Express19(6), 5172–5186 (2011). [CrossRef] [PubMed]
  4. A. Alduino, L. Liao, R. Jones, M. Morse, B. Kim, W. Lo, J. Basak, B. Koch, H. Liu, H. Rong, M. Sysak, C. Krause, R. Saba, D. Lazar, L. Horwitz, R. Bar, S. Litski, A. Liu, K. Sullivan, O. Dosunmu, N. Na, T. Yin, F. Haubensack, I. Hsieh, J. Heck, R. Beatty, H. Park, J. Bovington, S. Lee, H. Nguyen, H. Au, K. Nguyen, P. Merani, M. Hakami, and M. Paniccia, “Demonstration of a High Speed 4-Channel Integrated Silicon Photonics WDM Link with Hybrid Silicon Lasers,” Integrated Photonics Research, Silicon and Nano Photonics (IPR), PDIWI5 (2010).
  5. S. J. Koester, C. L. Schow, L. Schares, G. Dehlinger, J. D. Schaub, F. E. Doany, and R. A. John, “Ge-on-SOI-detector/Si-CMOS-amplifier receivers for high-performance optical communications applications,” J. Lightwave Technol.25(1), 46–57 (2007). [CrossRef]
  6. T. Takemoto, F. Yuki, H. Yamashita, S. Tsuji, Y. Lee, K. Adachi, K. Shinoda, Y. Matsuoka, K. Kogo, S. Nishimura, M. Nido, M. Namiwaka, T. Kaneko, T. Sugimoto, and K. Kurata, “100-Gbps CMOS Transceiver for Multilane Optical Backplane System with 1.3-cm2 Footprint, ” 37th European Conference and Exposition on Optical Communications (ECOC), Th.12.B.5. (2011).
  7. A. Narasimha, B. Analui, Y. Liang, T. J. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. G. M. P. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A fully integrated 4 × 10-Gb/s DWDM optoelectronic transceiver implemented in a standard 0.13 µm CMOS SOI technology,” IEEE J. Solid-state Circuits42(12), 2736–2744 (2007). [CrossRef]
  8. S. Assefa, F. Xia, S. W. Bedell, Y. Zhang, T. Topuria, P. M. Rice, and Y. A. Vlasov, “CMOS-integrated high-speed MSM germanium waveguide photodetector,” Opt. Express18(5), 4986–4999 (2010). [CrossRef] [PubMed]
  9. B. G. Lee, S. Assefa, C. Schow, W. M. Green, A. Rylyakov, R. A. John, J. A. Kash, and Y. A. Vlasov, “Hybrid-Integrated Germanium Photodetector and CMOS Receiver Operating at 15 Gb/s,” Conference on Lasers and Electro-Optics (CLEO), CFB4 (2011).
  10. Q. Fang, Y. T. Phang, C. W. Tan, T. Y. Liow, M. B. Yu, G. Q. Lo, and D. L. Kwong, “Multi-channel silicon photonic receiver based on ring-resonators,” Opt. Express18(13), 13510–13515 (2010). [CrossRef] [PubMed]
  11. C. L. Schow, A. V. Rylyakov, C. Baks, F. E. Doany, and J. A. Kash, “A 25 Gb/s, 6.5 pJ/bit, 90-nm CMOS-driven multimode optical link,” IEEE Photon. Technol. Lett.24(10), 824–826 (2012). [CrossRef]
  12. L. Chen, C. R. Doerr, L. Buhl, Y. Baeyens, and R. A. Aroca, “Monolithically integrated 40-wavelength demultiplexer and photodetector array on silicon,” IEEE Photon. Technol. Lett.23(13), 869–871 (2011). [CrossRef]
  13. A. V. Rylyakov, C. L. Schow, J. Proesel, D. M. Kuchta, C. Baks, N. Y. Li, C. Xie, and K. Jackson, “A 40-Gb/s, 850-nm, VCSEL-Based Full Optical Link,” Optical Fiber Communication Conference (OFC), OTh1E.1 (2012).
  14. C. F. Liao and S. Liu, “40 Gb/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90 nm CMOS,” IEEE J. Solid-state Circuits43(3), 642–655 (2008). [CrossRef]
  15. J. Kim and J. F. Buckwalter, “A 40-Gb/s optical transceiver front-end in 45 nm SOI CMOS,” IEEE J. Solid-state Circuits47(3), 615–626 (2012). [CrossRef]
  16. S. Assefa, W. M. Green, A. V. Rylyakov, C. L. Schow, F. Horst, and Y. A. Vlasov, “CMOS Integrated Silicon Nanophotonics: Enabling Technology for Exascale Computational Systems,” Optical Fiber Communication Conference (OFC), OMM6 (2011).
  17. W. M. Green, A. V. Rylyakov, C. L. Schow, F. Horst, and Y. A. Vlasov, “CMOS integrated Silicon Nanophotonics: Enabling Technology for Exascale Computational Systems,” Proc. SEMICON, Chiba, Japan, Dec. 1–3, 2010, available: http://www.research.ibm.com/photonics .
  18. S. Assefa, F. Xia, S. W. Bedell, Y. Zhang, T. Topuria, P. M. Rice, and Y. A. Vlasov, “CMOS-Integrated 40GHz Germanium Waveguide Photodetector for On-chip Optical Interconnects,” Optical Fiber Communication Conference (OFC), OMR4 (2009).
  19. S. Assefa, C. Jahnes, and Y. Vlasov, “CMOS compatible integrated dielectric optical waveguide coupler and fabrication,” US Patent 2009/0324162 A1, filed June 2008.

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