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Optics Express

Optics Express

  • Editor: C. Martijn de Sterke
  • Vol. 20, Iss. 26 — Dec. 10, 2012
  • pp: B256–B263
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Demonstration of 12.5-Gbps optical interconnects integrated with lasers, optical splitters, optical modulators and photodetectors on a single silicon substrate

Yutaka Urino, Yoshiji Noguchi, Masataka Noguchi, Masahiko Imai, Masashi Yamagishi, Shigeru Saitou, Naoki Hirayama, Masashi Takahashi, Hiroyuki Takahashi, Emiko Saito, Makoto Okano, Takanori Shimizu, Nobuaki Hatori, Masashige Ishizaka, Tsuyoshi Yamamoto, Takeshi Baba, Takeshi Akagawa, Suguru Akiyama, Tatsuya Usuki, Daisuke Okamoto, Makoto Miura, Junichi Fujikata, Daisuke Shimura, Hideaki Okayama, Hiroki Yaegashi, Tai Tsuchizawa, Koji Yamada, Masahiko Mori, Tsuyoshi Horikawa, Takahiro Nakamura, and Yasuhiko Arakawa  »View Author Affiliations


Optics Express, Vol. 20, Issue 26, pp. B256-B263 (2012)
http://dx.doi.org/10.1364/OE.20.00B256


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Abstract

One of the most serious issues in information industries is the bandwidth bottleneck in inter-chip interconnects. We propose a photonics-electronics convergence system to solve this issue. We fabricated a high density optical interposer to demonstrate the feasibility of the system by using silicon photonics integrated with an arrayed laser diode, an optical splitter, silicon optical modulators, germanium photodetectors, and silicon optical waveguides on a single silicon substrate. Error-free data transmission at 12.5 Gbps and a transmission density of 6.6 Tbps/cm2 were achieved with the optical interposer. We believe this technology will solve the bandwidth bottleneck problem in the future.

© 2012 OSA

1. Introduction

The CPU-CPU and CPU-memory inter-chip bandwidths in personal computers and servers are currently doubling every two years, and have been estimated to reach tera-scale by the mid 2010s [1

1. I. A. Young, E. M. Mohammed, J. T. S. Liao, A. M. Kem, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical technology for energy efficient I/O in high performance computing,” IEEE Commun. Mag. 48(10), 184–191 (2010). [CrossRef]

]. Although the wiring pitches in logic circuits are expected to shrink exponentially on the basis of Moore’s law, LSI I/O pad pitches, such as flip-chip pad pitches, are presently expected to remain large scale [2

2. International Technology Roadmap for Semiconductors 2009 Edition, Assembly and Packaging, Table AP2 and AP3. http://www.itrs.net/Links/2009ITRS/2009Chapters_2009Tables/2009_Assembly.pdf

]. Consequently, the scaling gap between intra- and inter-chips is going to widen annually. This is why the line speed for inter-chip interconnects in the future will need to be much higher than that for intra-chip ones. The required line speed is estimated to exceed 40 Gbps by the late 2010s, and currently there are no known solutions that are able to be manufactured with electrical interconnects [2

2. International Technology Roadmap for Semiconductors 2009 Edition, Assembly and Packaging, Table AP2 and AP3. http://www.itrs.net/Links/2009ITRS/2009Chapters_2009Tables/2009_Assembly.pdf

].

Optical interconnects with silicon photonics have been expected to be used as candidates for solving the bandwidth bottleneck problem with LSI chips and they have been researched by many organizations [1

1. I. A. Young, E. M. Mohammed, J. T. S. Liao, A. M. Kem, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical technology for energy efficient I/O in high performance computing,” IEEE Commun. Mag. 48(10), 184–191 (2010). [CrossRef]

, 3

3. L. Chen, K. Preston, S. Manipatruni, and M. Lipson, “Integrated GHz silicon photonic interconnect with micrometer-scale modulators and detectors,” Opt. Express 17(17), 15248–15256 (2009). [CrossRef] [PubMed]

6

6. X. Zheng, Y. Luo, J. Lexau, F. Liu, G. Li, H. Thacker, I. Shubin, J. Yao, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “2-pJ/bit (On-Chip) 10-Gb/s digital CMOS silicon photonic link,” IEEE Photon. Technol. Lett. 24(14), 1260–1262 (2012). [CrossRef]

] because of the intrinsic properties of optical signals, such as wide bandwidth, low latency, low power consumption, and low mutual interference, and the industrial advantages of silicon for use as resources in the electronics industry. However, there have been few reports on inter-chip interconnects achieved by using silicon photonics that have been fully integrated with light sources, optical modulators, and photodetectors (PDs) on a single silicon substrate.

2. Photonics-electronics convergence system for inter-chip interconnects

The conceptual model of the photonics-electronics convergence system for inter-chip interconnects is outlined in Fig. 1
Fig. 1 Conceptual model of photonics-electronics convergence system for inter-chip interconnects.
. The upper-left LSI chip on the silicon optical interposer has been removed to enable the substrate surface area that it covered to be seen. Arrayed LDs, optical splitters, optical modulators and PDs are integrated on a silicon substrate and are optically linked to each other via silicon optical waveguides. Together, they form an optical interposer. LSI bare chips are mounted on the interposer and are electrically connected to the optical modulators and PDs by flip-chip bonding. This system enables us to replace the function of conventional electronic wires on a printed circuit board (PCB) with the optical interconnects on a silicon substrate, which is one hundredth the size of a PCB. This silicon optical interposer has wide bandwidth capabilities due to the properties of its optical signals. Since the silicon substrates can be fabricated using a CMOS compatible process, they have quite high density and are low in cost. Furthermore, because this system is optically closed without any optical inputs or outputs, users do not have to worry about any optical issues (such as optical coupling, optical reflection, or polarization dependence).

3. Improvements to design and fabrication process of optical components

As stated in the introduction, we previously reported error-free data transmission at 5 Gbps and transmission density of 3.5 Tbps/cm2 by using a high density silicon optical interposer. We made some improvements in terms of the design and fabrication process to the optical components of the silicon optical interposer to achieve higher transmission density.

3.1 Improvements to fabrication process

3.2 Improvements to optical waveguides

3.3 Improvements to optical modulators

The optical modulator was a Mach-Zehnder interferometer composed of phase shifters and multimode interference (MMI) couplers. The phase shifters could change their refractive indices by using the carrier plasma effect in lateral P-I-N diode structures.

3.4 Improvements to photodetectors

3. 5 Improvements to spot-size converters

4. Data transmission experiments with integrated silicon optical interposers

We fabricated silicon optical interposers integrated with the improved optical components. There is a photograph of a fabricated silicon optical interposer in Fig. 7
Fig. 7 Photograph of fabricated silicon optical interposer.
. The substrate was 5 × 5 mm. A trident SSC array, a 1 × 4 optical splitter, an optical modulator array with side-wall gratings, and an MSM-PD array were monolithically integrated on a single silicon substrate, an arrayed LD chip was mounted on the substrate with a passive alignment technique, and these optical components were optically linked to each other via a silicon optical waveguide array. The LD chip was a 13-channel arrayed InGaAsP LD with a 30-μm channel pitch. Each channel was a Fabry-Perot type with a spot-size converter. The LD chip had a single pair of electrodes for all 13 channels that simultaneously emitted. The wavelength was 1530 nm.

The optical power budget per channel is summarized in Table 1

Table 1. Optical power budget

table-icon
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. The overall optical loss was 18 dB, including inherent 6-dB branching loss and 3-dB modulation loss. We could gain an optical power margin that enabled us to introduce the 1 × 4 optical splitter due to the novel trident SSC with quite low coupling loss. These results suggest that integrating a 13-channel arrayed LD, 13 1 × 4 optical splitters, 52 modulators and PDs enables the optical interposer to achieve a bandwidth of 650 Gbps on a single silicon substrate.

The footprints of optical components per channel are listed in Table 2

Table 2. Footprints of optical components per channel

table-icon
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. Thanks to the 1 × 4 optical splitter, the footprint of laser diode per channel was also split into four. The total footprint was 0.19 mm2 per channel, meaning we could achieve a transmission density of 6.6 Tbps/cm2 with a channel line rate of 12.5 Gbps. About two-thirds of the total footprint was occupied by electrode pads in these experiments. Therefore, we expect to improve the transmission density further with smaller pads in the near future.

6. Conclusion

We proposed a photonics-electronics convergence system with a silicon optical interposer by using silicon photonics in order to solve the bandwidth bottleneck problem that inter-chip interconnects have. We investigated the improvements to design and fabrication process of optical components for the silicon optical interposer: silicon optical waveguides, silicon optical modulators, germanium photodetectors, arrayed laser diodes, and spot-size converters. We then demonstrated the feasibility of the system by fabricating a high density optical interposer integrated with these optical components on a single silicon substrate. We achieved error-free data transmission at 12.5 Gbps and transmission density of 6.6 Tbps/cm2 with the optical interposer. We believe that this technology will solve the bandwidth bottleneck problem in the future.

Acknowledgments

This research is supported by the Japan Society for the Promotion of Science (JSPS) through its “Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program).” Part of the fabrication was conducted at the Nano-Processing Facility, supported by IBEC Innovation Platform, AIST.

References and links

1.

I. A. Young, E. M. Mohammed, J. T. S. Liao, A. M. Kem, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical technology for energy efficient I/O in high performance computing,” IEEE Commun. Mag. 48(10), 184–191 (2010). [CrossRef]

2.

International Technology Roadmap for Semiconductors 2009 Edition, Assembly and Packaging, Table AP2 and AP3. http://www.itrs.net/Links/2009ITRS/2009Chapters_2009Tables/2009_Assembly.pdf

3.

L. Chen, K. Preston, S. Manipatruni, and M. Lipson, “Integrated GHz silicon photonic interconnect with micrometer-scale modulators and detectors,” Opt. Express 17(17), 15248–15256 (2009). [CrossRef] [PubMed]

4.

K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE 7607, 1–16 (2010).

5.

G. Kim, J. W. Park, I. G. Kim, S. Kim, S. Kim, J. M. Lee, G. S. Park, J. Joo, K. S. Jang, J. H. Oh, S. A. Kim, J. H. Kim, J. Y. Lee, J. M. Park, D. W. Kim, D. K. Jeong, M. S. Hwang, J. K. Kim, K. S. Park, H. K. Chi, H. C. Kim, D. W. Kim, and M. H. Cho, “Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s,” Opt. Express 19(27), 26936–26947 (2011). [CrossRef] [PubMed]

6.

X. Zheng, Y. Luo, J. Lexau, F. Liu, G. Li, H. Thacker, I. Shubin, J. Yao, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “2-pJ/bit (On-Chip) 10-Gb/s digital CMOS silicon photonic link,” IEEE Photon. Technol. Lett. 24(14), 1260–1262 (2012). [CrossRef]

7.

Y. Urino, T. Shimizu, M. Okano, N. Hatori, M. Ishizaka, T. Yamamoto, T. Baba, T. Akagawa, S. Akiyama, T. Usuki, D. Okamoto, M. Miura, M. Noguchi, J. Fujikata, D. Shimura, H. Okayama, T. Tsuchizawa, T. Watanabe, K. Yamada, S. Itabashi, E. Saito, T. Nakamura, and Y. Arakawa, “First demonstration of high density optical interconnects integrated with lasers, optical modulators, and photodetectors on single silicon substrate,” Opt. Express 19(26), B159–B165 (2011). [CrossRef] [PubMed]

8.

N. Hirayama, H. Takahashi, Y. Noguchi, M. Yamagishi, and T. Horikawa, “Low-loss Si waveguides with variable-shaped-beam EB lithography for large-scaled photonic circuits,” The extended abstract of 2012 International Conference on Solid State Devices and Materials (SSDM), A-2–2 (2012).

9.

S. Akiyama, T. Baba, M. Imai, T. Akagawa, M. Takahashi, N. Hirayama, H. Takahashi, Y. Noguchi, H. Okayama, T. Horikawa, and T. Usuki, “12.5-Gb/s operation with 0.29-V•cm V(π)L using silicon Mach-Zehnder modulator based-on forward-biased pin diode,” Opt. Express 20(3), 2911–2923 (2012). [CrossRef] [PubMed]

10.

J. Fujikata, M. Noguchi, M. Miura, D. Okamoto, T. Horikawa, and Y. Arakawa, “Si waveguide-integrated MSM Ge photodiode,” Proceeding of International Conference on Solid State Devices and Materials (SSDM), CI-6–3 (2011).

11.

N. Hatori, T. Shimizu, M. Okano, M. Ishizaka, T. Yamamoto, Y. Urino, M. Mori, T. Nakamura, and Y. Arakawa, “A novel spot size convertor for hybrid integrated light sources on photonics-electronics convergence system,” Proceeding of 9th International Conference on Group IV Photonics (GFP), ThB2 (2012).

12.

N. Fujioka, T. Chu, and M. Ishizaka, “Compact and low power consumption hybrid integrated wavelength tunable laser module using silicon waveguide resonators,” J. Lightwave Technol. 28, 3115–3120 (2010).

OCIS Codes
(130.3120) Integrated optics : Integrated optics devices
(200.4650) Optics in computing : Optical interconnects

ToC Category:
Waveguide and Optoelectronic Devices

History
Original Manuscript: September 28, 2012
Revised Manuscript: November 11, 2012
Manuscript Accepted: November 12, 2012
Published: November 29, 2012

Virtual Issues
European Conference on Optical Communication 2012 (2012) Optics Express

Citation
Yutaka Urino, Yoshiji Noguchi, Masataka Noguchi, Masahiko Imai, Masashi Yamagishi, Shigeru Saitou, Naoki Hirayama, Masashi Takahashi, Hiroyuki Takahashi, Emiko Saito, Makoto Okano, Takanori Shimizu, Nobuaki Hatori, Masashige Ishizaka, Tsuyoshi Yamamoto, Takeshi Baba, Takeshi Akagawa, Suguru Akiyama, Tatsuya Usuki, Daisuke Okamoto, Makoto Miura, Junichi Fujikata, Daisuke Shimura, Hideaki Okayama, Hiroki Yaegashi, Tai Tsuchizawa, Koji Yamada, Masahiko Mori, Tsuyoshi Horikawa, Takahiro Nakamura, and Yasuhiko Arakawa, "Demonstration of 12.5-Gbps optical interconnects integrated with lasers, optical splitters, optical modulators and photodetectors on a single silicon substrate," Opt. Express 20, B256-B263 (2012)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-20-26-B256


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References

  1. I. A. Young, E. M. Mohammed, J. T. S. Liao, A. M. Kem, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical technology for energy efficient I/O in high performance computing,” IEEE Commun. Mag.48(10), 184–191 (2010). [CrossRef]
  2. International Technology Roadmap for Semiconductors 2009 Edition, Assembly and Packaging, Table AP2 and AP3. http://www.itrs.net/Links/2009ITRS/2009Chapters_2009Tables/2009_Assembly.pdf
  3. L. Chen, K. Preston, S. Manipatruni, and M. Lipson, “Integrated GHz silicon photonic interconnect with micrometer-scale modulators and detectors,” Opt. Express17(17), 15248–15256 (2009). [CrossRef] [PubMed]
  4. K. Raj, J. E. Cunningham, R. Ho, X. Zheng, H. Schwetman, P. Koka, M. McCracken, J. Lexau, G. Li, H. Thacker, I. Shubin, Y. Luo, J. Yao, M. Asghari, T. Pinguet, J. Mitchell, and A. V. Krishnamoorthy, “’Macrochip’ computer systems enabled by silicon photonic interconnects,” Proc. SPIE7607, 1–16 (2010).
  5. G. Kim, J. W. Park, I. G. Kim, S. Kim, S. Kim, J. M. Lee, G. S. Park, J. Joo, K. S. Jang, J. H. Oh, S. A. Kim, J. H. Kim, J. Y. Lee, J. M. Park, D. W. Kim, D. K. Jeong, M. S. Hwang, J. K. Kim, K. S. Park, H. K. Chi, H. C. Kim, D. W. Kim, and M. H. Cho, “Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s,” Opt. Express19(27), 26936–26947 (2011). [CrossRef] [PubMed]
  6. X. Zheng, Y. Luo, J. Lexau, F. Liu, G. Li, H. Thacker, I. Shubin, J. Yao, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “2-pJ/bit (On-Chip) 10-Gb/s digital CMOS silicon photonic link,” IEEE Photon. Technol. Lett.24(14), 1260–1262 (2012). [CrossRef]
  7. Y. Urino, T. Shimizu, M. Okano, N. Hatori, M. Ishizaka, T. Yamamoto, T. Baba, T. Akagawa, S. Akiyama, T. Usuki, D. Okamoto, M. Miura, M. Noguchi, J. Fujikata, D. Shimura, H. Okayama, T. Tsuchizawa, T. Watanabe, K. Yamada, S. Itabashi, E. Saito, T. Nakamura, and Y. Arakawa, “First demonstration of high density optical interconnects integrated with lasers, optical modulators, and photodetectors on single silicon substrate,” Opt. Express19(26), B159–B165 (2011). [CrossRef] [PubMed]
  8. N. Hirayama, H. Takahashi, Y. Noguchi, M. Yamagishi, and T. Horikawa, “Low-loss Si waveguides with variable-shaped-beam EB lithography for large-scaled photonic circuits,” The extended abstract of 2012 International Conference on Solid State Devices and Materials (SSDM), A-2–2 (2012).
  9. S. Akiyama, T. Baba, M. Imai, T. Akagawa, M. Takahashi, N. Hirayama, H. Takahashi, Y. Noguchi, H. Okayama, T. Horikawa, and T. Usuki, “12.5-Gb/s operation with 0.29-V•cm V(π)L using silicon Mach-Zehnder modulator based-on forward-biased pin diode,” Opt. Express20(3), 2911–2923 (2012). [CrossRef] [PubMed]
  10. J. Fujikata, M. Noguchi, M. Miura, D. Okamoto, T. Horikawa, and Y. Arakawa, “Si waveguide-integrated MSM Ge photodiode,” Proceeding of International Conference on Solid State Devices and Materials (SSDM), CI-6–3 (2011).
  11. N. Hatori, T. Shimizu, M. Okano, M. Ishizaka, T. Yamamoto, Y. Urino, M. Mori, T. Nakamura, and Y. Arakawa, “A novel spot size convertor for hybrid integrated light sources on photonics-electronics convergence system,” Proceeding of 9th International Conference on Group IV Photonics (GFP), ThB2 (2012).
  12. N. Fujioka, T. Chu, and M. Ishizaka, “Compact and low power consumption hybrid integrated wavelength tunable laser module using silicon waveguide resonators,” J. Lightwave Technol.28, 3115–3120 (2010).

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