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Optics Express

Optics Express

  • Editor: C. Martijn de Sterke
  • Vol. 20, Iss. 26 — Dec. 10, 2012
  • pp: B7–B14
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Demonstration of low-power bit-interleaving TDM PON

Christophe Van Praet, Hungkei Chow, Dusan Suvakovic, Doutje Van Veen, Arnaud Dupas, Roger Boislaigue, Robert Farah, Man Fai Lau, Joseph Galaro, Gin Qua, N. Prasanth Anthapadmanabhan, Guy Torfs, Xin Yin, and Peter Vetter  »View Author Affiliations


Optics Express, Vol. 20, Issue 26, pp. B7-B14 (2012)
http://dx.doi.org/10.1364/OE.20.0000B7


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Abstract

A functional demonstration of bit-interleaving TDM downstream protocol for passive optical networks (Bi-PON) is reported. The proposed protocol presents a significant reduction in dynamic power consumption in the customer premise equipment over the conventional TDM protocol. It allows to select the relevant bits of all aggregated incoming data immediately after clock and data recovery (CDR) and, hence, allows subsequent hardware to run at much lower user rate. Comparison of experimental results of FPGA-based implementations of Bi-PON and XG-PON shows that more than 30x energy-savings in protocol processing is achievable.

© 2012 OSA

1. Introduction

This work focuses on the energy consumption of optical access networks, passive optical networks (PONs) in particular. In a PON, an optical line terminal (OLT) at the central office is connected to a number of optical network terminations (ONTs) at the customer premises, typically 32 to 128, over a shared fiber plant. The total power consumption of a PON is dominated by the ONTs simply because of their volume.

Most PONs deployed today adopt a time-division-multiplexing (TDM) scheme as an access mechanism on the shared medium. TDM-based protocols have been specified by the standard bodies [4

4. Telecommunication standardization sector of International telecommunication union (ITU-T), GPON Standards G.984 series.

, 5

5. Telecommunication standardization sector of International telecommunication union (ITU-T), 10-Gigabit-capable passive optical network (XG-PON) systems: Definitions, abbreviations, and acronyms G.987.

]. To cope with the increasing bandwidth demand, these protocols have also evolved with a higher line rate [4

4. Telecommunication standardization sector of International telecommunication union (ITU-T), GPON Standards G.984 series.

, 5

5. Telecommunication standardization sector of International telecommunication union (ITU-T), 10-Gigabit-capable passive optical network (XG-PON) systems: Definitions, abbreviations, and acronyms G.987.

]. These “super-charged” protocols, however, suffer from the problem of energy inefficiency which is inherited from their predecessors. As the line rates have increased, this problem has become noticeable.

This paper is an expanded version of our publication at ECOC 2012 [7

7. H. Chow, D. Suvakovic, D. Van Veen, A. Dupas, R. Boislaigue, R. Farah, M. F. Lau, J. Galaro, G. Qua, N. P. Anthapadmanabhan, G. Torfs, C. Van Praet, X. Yin, and P. Vetter, “Demonstration of low-Power bit-Interleaving TDM PON,” 38th European Conference and Exhibition on Optical Communication, Mo.2.B.1 (2012).

]. In this paper, the Bi-PON protocol is discussed in more detail and the architecture of the Bi-PON ONT is disclosed to better explain how the protocol facilitates considerable energy savings to be realized. In addition, experimental results with our recently developed bit-interleaving CDR (Bi-CDR) ASIC [8

8. C. Van Praet, G. Torfs, Z. Li, X. Yin, D. Suvakovic, H. Chow, X.-Z. Qiu, and P. Vetter, “A 10 Gb/s bit interleaving CDR for low-power PON,” Electron. Lett. 48(21), 1361–1363 (2012). [CrossRef]

] are compared with XG-PON and an FPGA-based implementation of Bi-PON.

2. Energy deficiencies of XG-PON protocol

Fig. 1 Downstream architecture of XG-PON ONT

This paper only focuses on the downstream protocol because it largely dominates the total power consumption of an ONT. The upstream data path is considered energy efficient given that there is no unrelated traffic being processed. The burst-mode behavior at the upstream transmission is also inherently energy efficient.

3. The bit-interleaving PON protocol (Bi-PON)

To overcome the issue in XG-PON protocol, this paper proposes a Bi-PON protocol which modifies the framing structure of the transmission. Figure 2 explains how the protocol works, different colors are used to denote bits intended for different ONTs. The Bi-PON frame has a fixed length of 125 μs corresponding to the XG-PON frame. It consists of a header section and a payload section. The header section is further divided into a synchronization field, a bandwidth map field and an operation, administration and maintenance (OAM) field. The main distinguishing feature of the Bi-PON frame is that all information bits residing in all sections are organized in a bit-interleaved fashion according to the targeted ONTs. This scheme contrasts the XG-PON framing where groups of information bits targeted to a particular ONT are placed in various, irregularly spread locations in a frame. Because of this regular structure in a Bi-PON frame, each ONT only needs to extract its own information in a simple periodic fashion.

Fig. 2 Bi-PON transmission frame structure

Figure 3 shows a block diagram of the Bi-PON ONT downstream operations. As becomes clear when comparing Fig. 1 and Fig. 3, the number of functional blocks required to operate at full line rate has been reduced significantly. Immediately after the conversion of the incoming optical signal into the electrical domain by the O/E front-end receiver, the clock and data recovery (CDR) circuit extracts the clocking/timing information and recovers the raw information bits. The Bi-PON protocol supports a fixed number of ONTs, e.g. 256. By matching a synchronization pattern and its own ONT identifier, an ONT only need to “listen” to one of the 256 ONT-channels. The bit-interleaving structure together with the fixed number of ONTs reduces the decimation operation into a simple down-sampler. This contrasts to a more complex de-serialization and word alignment operation found in the XG-PON protocol. And, more importantly, the information rate after the decimator is significantly reduced, from the line rate (i.e., 10 Gb/s) to the user rate, typically below 1 Gb/s as bits intended for other users are immediately discarded. This allows all subsequent operations to be run at a much lower clock rate than the ones in XG-PON. Hence, dynamic power consumption of a Bi-PON ONT is significantly lower.

Fig. 3 Downstream architecture of Bi-PON ONT

While the bit allocation scheme in the header section is fixed, the Bi-PON protocol adopts a flexible dynamic bandwidth allocation (DBA) mechanism in the payload section. Within the BW map field, it carries bandwidth allocation information specified as a tuple (Si, Ki) where Ki is the sampling rate and Si is the starting offset of an ONT i. Based on this information, the decimator can extract the payload bits that belong to the designated ONT in the payload section. As the OLT composes (Si, Ki) for all ONTs, it may update this allocation in a frame by frame basis according to the instantaneous traffic profile of the ONTs.

As illustrated in Fig. 2, the protocol also includes an OAM field in the header. The OAM field carries commands such as ranging, encryption keys, etc. A useful OAM command is the “SLEEP CMD” in which the target ONT is instructed to enter a sleep state for the duration of time specified in command argument (in terms of number of frames). During the sleep duration, an ONT shuts off most of the downstream operation except the CDR, decimator and bit-counter to save energy.

4. Processing a Bi-PON frame

Fig. 4 Flow-chart of Bi-PON frame processing

5. Experimental results

As an experiment, we have prototyped a basic Bi-PON ONT using an FPGA based design as shown in Fig. 5(a). This design uses an Altera Stratix IV EP4SGX230 device, a 10 Gb/s CDR from Vitesse and off-the-shelf XG-PON transceiver components. For comparison, we have also implemented a basic XG-PON ONT on the same hardware, to allow a fair comparison. Apart from the FEC decoder and decryption modules, the basic ONTs implement all functional modules, as those shown in Fig. 1 and Fig. 3.

Fig. 5 Experimental prototypes

Additionally, an ASIC based prototype of the Bi-PON ONT, as shown in Fig. 5(b), was designed using our bit-interleaving CDR [8

8. C. Van Praet, G. Torfs, Z. Li, X. Yin, D. Suvakovic, H. Chow, X.-Z. Qiu, and P. Vetter, “A 10 Gb/s bit interleaving CDR for low-power PON,” Electron. Lett. 48(21), 1361–1363 (2012). [CrossRef]

] to demonstrate its absolute energy efficiency. This ASIC was fabricated in a 0.13μm BiCMOS process and incorporates a PLL-based CDR. The same XG-PON transceiver components were used as in the previously described FPGA-based implementations. The interworking function (IWF) and user network interface (UNI), medium access control/physical coding sublayer and physical medium dependent sublayer (MAC/PCS/PMD) were implemented on a low-power Xilinx Kintex-7 FPGA, so the ASIC-based Bi-PON ONT has the same functionality as the the one shown in Fig. 5(a).

For the discussion of measurement results, only the downstream path is considered. Comparing the two FPGA-based implementations, the Bi-PON ONT design utilizes significantly less logic and memory resources than the XG-PON ONT design. This is mainly due to the simplified protocol with its ability to greatly reduce the data rate of the incoming data stream to its useful content, very early in the architecture. This reduction in data rate eliminates the requirement of massive parallel data paths and operations. As a result, both dynamic and static power consumption of the Bi-PON ONT are lower than the XG-PON ONT.

As FPGAs are known to have high static power consumption, in order to fairly compare the energy efficiency of two protocols, we have adopted the following methodology to estimate dynamic power consumption. In our experiment, we first measured the power consumption of the board when the input line is removed and all clocks on the board are disabled. This measurement represents a baseline idle (or static) power consumption of the design. Then, we measured the power consumption of a fully operational design at various traffic load conditions. The difference in measured power between a fully operational state and an idle state yields the estimated dynamic power consumption. Dynamic power consumption is a good indicator of the potential savings in the future custom chip design.

Table 1 compares the dynamic power consumption measurements of both FPGA-based designs at different traffic loads, ranging from 1.25Gb/s, over 10Mb/s to “idle” where there is no traffic load (“without sleep” refers to the scenario where there is no bandwidth map, “with sleep” refers to situation where the OAM field signals the ONT to be inactive for a given time and to power down hardware accordingly). It also lists the results of this measurement on the ASIC-based design as reference. The figures for the FPGA-based ONT’s also include the dynamic power consumption of the Vitesse CDR, which is estimated to be about 98 mW. When comparing both FPGA implementations, we notice, as expected, that the ONT implementing the XG-PON protocol suffers from a much higher dynamic power consumption than the one implementing the Bi-PON protocol. At a traffic load of 1.25 Gb/s, a Bi-PON ONT exhibits a ∼18x power saving compared to the XG-PON ONT, including the Vitesse CDR. This increases to ∼35x when subtracting the power of the CDR. It is also observed that dynamic power consumption of XG-PON does not vary much (or varies within the margin of error in our measurements) at various loading conditions. This is expected since the majority of the operations do not change as the traffic condition varies. For Bi-PON, however, the dynamic power consumption decreases with the reduction of bandwidth allocation. Recall that dynamic power consumption of a CMOS circuit is proportional to its operating frequency. As the operating frequency of functional modules behind the decimator is scaled down, the power consumption is reduced accordingly. At a traffic load of 10 Mb/s, the Bi-PON ONT exhibits a ∼180x power saving in protocol processing compared to the XG-PON ONT (without considering the CDR).

Table 1. Estimated dynamic power consumption [W]

table-icon
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As also indicated in Table 1, introducing the sleep mode operation in XG-PON does reduce its power consumption by ∼28%. However, this reduction is not as significant as one would expect because several key modules in the design cannot be completely shut down without losing their states. In contrast, in a Bi-PON ONT, when there is no BW allocation or when the ONT is in sleep state, most functional modules are inherently shut off as there is no clock or data output from the decimator.

A graph of the dynamic power consumption of both Bi-PON implementations in function of the user data rate is shown in Fig. 6. It is interesting to notice that power dissipation of the Bi-PON ONTs scales well with the user data rate. The static power consumption of the ASIC itself amounts to approximately 130 mW [8

8. C. Van Praet, G. Torfs, Z. Li, X. Yin, D. Suvakovic, H. Chow, X.-Z. Qiu, and P. Vetter, “A 10 Gb/s bit interleaving CDR for low-power PON,” Electron. Lett. 48(21), 1361–1363 (2012). [CrossRef]

]. Migration to a deep sub-micron CMOS technology would allow to further decrease both dynamic and static power consumption as more logic could be implemented in plain CMOS. For the complete test-boards, the static power consumption amounts to 9.5 W for the FPGA-based Bi-PON ONT and 2.9 W for the ASIC-based version.

Fig. 6 Strong relationship between dissipation and data rate for Bi-PON

6. Conclusions

Acknowledgments

This work was supported by GreenTouch, Alcatel-Lucent, IMEC and Ghent University.

References and links

1.

G. Yeap, Practical Low Power Digital VLSI Design (Kluwer Academic Publishers, 1998).

2.

D. C. Kilper, G. Atkinson, S. K. Korotky, S. Goyal, P. Vetter, D. Suvakovic, and O. Blume, “Power trends in communication networks,” IEEE J. Sel. Top. Quantum Electron. 17(2), 275–284 (2011). [CrossRef]

3.

P. Vetter, L. Lefevre, L. Gasca, K. Kanonakis, L. Kazovsky, A. Lee, C. Monney, X. Qiu, F. Saliou, and A. Wonfor, “Research roadmap for green wireline access,” Workshop on Green Communications and Networking during IEEE ICC’12, Ottawa, Canada, Jun. 2012.

4.

Telecommunication standardization sector of International telecommunication union (ITU-T), GPON Standards G.984 series.

5.

Telecommunication standardization sector of International telecommunication union (ITU-T), 10-Gigabit-capable passive optical network (XG-PON) systems: Definitions, abbreviations, and acronyms G.987.

6.

D. Suvakovic, H. Chow, D. Van Veen, J. Galaro, B. Farah, N. P. Anthapadmanabhan, P. Vetter, A. Dupas, and R. Boislaigue, “Low energy bit-interleaving downstream protocol for passive optical networks, ” in Proceedings of IEEE Online Conference on Green Communications (Institute of Electrical and Electronics Engineers, 2012), pp. 104–109.

7.

H. Chow, D. Suvakovic, D. Van Veen, A. Dupas, R. Boislaigue, R. Farah, M. F. Lau, J. Galaro, G. Qua, N. P. Anthapadmanabhan, G. Torfs, C. Van Praet, X. Yin, and P. Vetter, “Demonstration of low-Power bit-Interleaving TDM PON,” 38th European Conference and Exhibition on Optical Communication, Mo.2.B.1 (2012).

8.

C. Van Praet, G. Torfs, Z. Li, X. Yin, D. Suvakovic, H. Chow, X.-Z. Qiu, and P. Vetter, “A 10 Gb/s bit interleaving CDR for low-power PON,” Electron. Lett. 48(21), 1361–1363 (2012). [CrossRef]

9.

K. Gallo and G. Assanto, “All-optical diode based on second-harmonic generation in an asymmetric waveguide,” J. Opt. Soc. Am. B 16, 267–269 (1999). [CrossRef]

10.

R. Kubo, J. Kani, H. Ujikawa, T. Sakamoto, Y. Fujimoto, N. Yoshimoto, and H. Hadama, “Study and demonstration of sleep and adaptive link rate control mechanisms for energy efficient 10G-EPON,” IEEE J. Opt. Commun. Netw. 2(9), 716–729 (2010). [CrossRef]

OCIS Codes
(060.0060) Fiber optics and optical communications : Fiber optics and optical communications
(060.2360) Fiber optics and optical communications : Fiber optics links and subsystems

ToC Category:
Access Networks and LAN

History
Original Manuscript: September 28, 2012
Revised Manuscript: November 5, 2012
Manuscript Accepted: November 8, 2012
Published: November 28, 2012

Virtual Issues
European Conference on Optical Communication 2012 (2012) Optics Express

Citation
Christophe Van Praet, Hungkei Chow, Dusan Suvakovic, Doutje Van Veen, Arnaud Dupas, Roger Boislaigue, Robert Farah, Man Fai Lau, Joseph Galaro, Gin Qua, N. Prasanth Anthapadmanabhan, Guy Torfs, Xin Yin, and Peter Vetter, "Demonstration of low-power bit-interleaving TDM PON," Opt. Express 20, B7-B14 (2012)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-20-26-B7


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References

  1. G. Yeap, Practical Low Power Digital VLSI Design (Kluwer Academic Publishers, 1998).
  2. D. C. Kilper, G. Atkinson, S. K. Korotky, S. Goyal, P. Vetter, D. Suvakovic, and O. Blume, “Power trends in communication networks,” IEEE J. Sel. Top. Quantum Electron.17(2), 275–284 (2011). [CrossRef]
  3. P. Vetter, L. Lefevre, L. Gasca, K. Kanonakis, L. Kazovsky, A. Lee, C. Monney, X. Qiu, F. Saliou, and A. Wonfor, “Research roadmap for green wireline access,” Workshop on Green Communications and Networking during IEEE ICC’12, Ottawa, Canada, Jun. 2012.
  4. Telecommunication standardization sector of International telecommunication union (ITU-T), GPON Standards G.984 series.
  5. Telecommunication standardization sector of International telecommunication union (ITU-T), 10-Gigabit-capable passive optical network (XG-PON) systems: Definitions, abbreviations, and acronyms G.987.
  6. D. Suvakovic, H. Chow, D. Van Veen, J. Galaro, B. Farah, N. P. Anthapadmanabhan, P. Vetter, A. Dupas, and R. Boislaigue, “Low energy bit-interleaving downstream protocol for passive optical networks, ” in Proceedings of IEEE Online Conference on Green Communications (Institute of Electrical and Electronics Engineers, 2012), pp. 104–109.
  7. H. Chow, D. Suvakovic, D. Van Veen, A. Dupas, R. Boislaigue, R. Farah, M. F. Lau, J. Galaro, G. Qua, N. P. Anthapadmanabhan, G. Torfs, C. Van Praet, X. Yin, and P. Vetter, “Demonstration of low-Power bit-Interleaving TDM PON,” 38th European Conference and Exhibition on Optical Communication, Mo.2.B.1 (2012).
  8. C. Van Praet, G. Torfs, Z. Li, X. Yin, D. Suvakovic, H. Chow, X.-Z. Qiu, and P. Vetter, “A 10 Gb/s bit interleaving CDR for low-power PON,” Electron. Lett.48(21), 1361–1363 (2012). [CrossRef]
  9. K. Gallo and G. Assanto, “All-optical diode based on second-harmonic generation in an asymmetric waveguide,” J. Opt. Soc. Am. B16, 267–269 (1999). [CrossRef]
  10. R. Kubo, J. Kani, H. Ujikawa, T. Sakamoto, Y. Fujimoto, N. Yoshimoto, and H. Hadama, “Study and demonstration of sleep and adaptive link rate control mechanisms for energy efficient 10G-EPON,” IEEE J. Opt. Commun. Netw.2(9), 716–729 (2010). [CrossRef]

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