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Optics Express

Optics Express

  • Editor: C. Martijn de Sterke
  • Vol. 20, Iss. 27 — Dec. 17, 2012
  • pp: 28153–28162
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An integrated 12.5-Gb/s optoelectronic receiver with a silicon avalanche photodetectorin standard SiGe BiCMOS technology

Jin-Sung Youn, Myung-Jae Lee, Kang-Yeob Park, Holger Rücker, and Woo-Young Choi  »View Author Affiliations


Optics Express, Vol. 20, Issue 27, pp. 28153-28162 (2012)
http://dx.doi.org/10.1364/OE.20.028153


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Abstract

An optoelectronic integrated circuit (OEIC) receiver is realized with standard 0.25-μm SiGe BiCMOS technology for 850-nm optical interconnect applications. The OEIC receiver consists of a Si avalanche photodetector, a transimpedance amplifier with a DC-balanced buffer, a tunable equalizer, and a limiting amplifier. The fabricated OEIC receiver successfully detects 12.5-Gb/s 231-1 pseudorandom bit sequence optical data with the bit-error rate less than 10−12 at incident optical power of −7 dBm. The OEIC core has 1000 μm x 280 μm chip area, and consumes 59 mW from 2.5-V supply. To the best of our knowledge, this OEIC receiver achieves the highest data rate with the smallest sensitivity as well as the best power efficiency among integrated OEIC receivers fabricated with standard Si technology.

© 2012 OSA

1. Introduction

For short-reach applications such as backplane or board-to-board interconnects, high-bandwidth interconnect solutions with cost effectiveness are highly desirable. One promising solution is optical interconnects based on 850-nm vertical-cavity surface-emitting lasers (VCSELs) and multimode fibers (MMFs) [1

1. T.-K. Woodward and A. V. Krishnamoorthy, “1-Gb/s integrated optical detectors and receivers in commercial CMOS technologies,” IEEE J. Sel. Top. Quantum Electron. 5(2), 146–156 (1999). [CrossRef]

]. VCSELs can be cheaper than edge-emitting lasers, and MMFs with the larger core size allow more cost-effective packaging solutions. On top of this, Si optoelectronic integrated circuit (OEIC) receivers including monolithically integrated 850-nm Si photodetectors (PDs) realized with standard Si technology is very attractive as they can take a full advantage of powerful Si technology and also achieve better performance by eliminating parasitic pad capacitance and bonding wire inductance unavoidable in hybrid approaches [2

2. A. C. Carusone, H. Yasotharan, and T. Kao, “CMOS technology scaling considerations for multi-gbps optical receivers with integrated photodetectors,” IEEE J. Solid-state Circuits 46(8), 1832–1842 (2011). [CrossRef]

].

However, PDs realized with standard Si technology have low detection efficiency due to shallow PN junctions provided by the standard Si technology when 850-nm light has much larger absorption length. Furthermore, their detection bandwidth is limited by slow diffusion of photogenerated carriers in the charge neutral region [3

3. S. Radovanovic, A.-J. Annema, and B. Nauta, “A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication,” IEEE J. Solid-state Circuits 40(8), 1706–1717 (2005). [CrossRef]

]. To overcome these problems while maintaining the advantage of using the standard Si technology, various types of PDs have been investigated [4

4. B. Nakhkoob, S. Ray, and M. M. Hella, “High speed photodiodes in standard nanometer scale CMOS technology: a comparative study,” Opt. Express 20(10), 11256–11270 (2012). [CrossRef] [PubMed]

]. Among these, spatially-modulated light (SML) PDs based on N-well/P-substrate junction have been widely used for OEIC receivers [5

5. M. Jutzi, M. Grözing, E. Gaugler, W. Mazioschek, and M. Berroth, “2-Gb/s CMOS optical integrated receiver with a spatially modulated photodetector,” IEEE Photon. Technol. Lett. 17(6), 1268–1270 (2005). [CrossRef]

10

10. S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-μm CMOS technology,” IEEE J. Solid-state Circuits 46(5), 1158–1169 (2011). [CrossRef]

] because SML PDs can provide enhanced detection bandwidth by eliminating slow diffusion currents. However, these PDs suffer from large optical loss because they inherently have the blocked area for differential operation. We have developed high-performance Si avalanche photodetectors (Si APDs) based on P+/N-well or N+/P-well junction realized with standard Si technology. These Si APDs provide high responsivity as well as large photodetection bandwidth [11

11. H.-S. Kang, M.-J. Lee, and W.-Y. Choi, “Si avalanche photodetectors fabricated in standard complementary metal-oxide-semiconductor process,” Appl. Phys. Lett. 90(15), 151118 (2007). [CrossRef]

], achieving larger than 1 THz gain-bandwidth product [12

12. M.-J. Lee and W.-Y. Choi, “A silicon avalanche photodetector fabricated with standard CMOS technology with over 1 THz gain-bandwidth product,” Opt. Express 18(23), 24189–24194 (2010). [CrossRef] [PubMed]

]. Furthermore, we have realized CMOS OEIC receivers with monolithically integrated Si APDs, which achieved 10-Gb/s operation with low power consumption and a small chip area [13

13. J.-S. Youn, M.-J. Lee, K.-Y. Park, and W.-Y. Choi, “10-Gb/s 850-nm CMOS OEIC receiver with a silicon avalanche photodetector,” IEEE J. Quantum Electron. 48(2), 229–236 (2012). [CrossRef]

].

In this paper, we present an 850-nm OEIC receiver fabricated with IHP’s standard 0.25-μm SiGe:C BiCMOS technology [14

14. B. Heinemann, R. Barth, D. Knoll, H. Rücker, B. Tillack, and W. Winkler, “High-performance BiCMOS technologies without epitaxially-buried subcollectors and deep trenches,” Semicond. Sci. Technol. 22(1), 153–157 (2007). [CrossRef]

]. In order to achieve high-speed operation, a Si APD having large photodetection bandwidth is monolithically integrated, and the receiver bandwidth is further enhanced with an equalizer (EQ) circuit. OEIC receivers in standard SiGe BiCMOS technology is of great interest since this technology has a potential for realizing integrated Ge PDs that are needed for 1.5-μm Si electronic-photonic ICs [15

15. D. Kucharski, D. Guckenberger, G. Masini, S. Abdalla, J. Witzens, and S. Sahni, “10Gb/s 15mW optical receiver with integrated germanium photodetector and hybrid inductor peaking in 0.13 μm SOI CMOS technology,” in Proceedings of IEEE International Solid-State Circuits Conference (IEEE, 2010), pp. 360–361.

]. An initial version of this work was reported in [16

16. J.-S. Youn, M.-J. Lee, K.-Y. Park, H. Rücker, and W.-Y. Choi, “A 12.5-Gb/s SiGe BiCMOS optical receiver with a monolithically integrated 850-nm avalanche photodetector,” in Proceedings of Optical Fiber Communication Conference (2012), paper OM3E2.

]. In this paper, we have included details of Si APD device characteristics and receiver circuits. Furthermore, we have added measured bit-error rate (BER) dependence on EQ boosting gain and APD reverse bias voltages.

2. SiGe BiCMOS OEIC receiver

Figure 1
Fig. 1 Simplified block diagram of the proposed OEIC receiver.
shows a simplified block diagram of our OEIC receiver. It is composed of a Si APD with a dummy PD, a shunt-feedback transimpedance amplifier (TIA) with DC-balanced buffer, a tunable EQ, a limiting amplifier (LA), and an output buffer with 50-Ω loads. The dummy PD having the same structure as the main Si APD is used to provide identical capacitance for differential TIA inputs. Both N-well contacts of the Si APD and dummy PD are tied with on-chip metal, and a positive voltage (VPD) of about 14.2 V, found to give the best OEIC receiver BER performance, is applied to N-well contacts, which results in reverse bias voltage (VR) of about 12 V for Si APD.

2.1 Silicon avalanche photodetector

Figure 2
Fig. 2 (a) Cross-section view and (b) top view of the fabricated Si APD.
shows simplified the cross-section and top view of the fabricated Si APD. It is implemented by P+ source/drain and N-well junction available in the BiCMOS technology. No design rule is violated for our APD implementation. The vertical PN junction is surrounded by shallow trench isolation in order to achieve large and uniform electric fields at the junction [17

17. M.-J. Lee, H. Rücker, and W.-Y. Choi, “Effects of guard-ring structures on the performance of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Electron Device Lett. 33(1), 80–82 (2012). [CrossRef]

]. Photogenerated currents are extracted from P+ contacts and delivered to the TIA. The Si APD has active area of about 10 μm x 10 μm with estimated junction capacitance of 35 fF. The junction capacitance (Cj) is estimated using Cj=εsA/WD where εs is the semiconductor permittivity, A is the cross-sectional area, and WD is the depletion width. P+/N-well depletion width in our Si APD is about 0.3 μm at VR of 12 V. This estimation is also verified by using an equivalent circuit model, in which the model parameters are extracted from the measured two-port S-parameter characteristics of our Si APD.

Figure 3(a)
Fig. 3 (a) Current-voltage characteristics, (b) responsivity and avalanche gain, and (c) photodetection frequency response of our Si APD.
shows the measured current-voltage characteristics as a function of VR with and without light injection. Figure 3(b) shows responsivity and avalanche gain as a function of VR at the incident optical power (Popt) of −10 dBm. Avalanche gain (G) at a given VR is defined as
G(VR)=Ilight(VR)Idark(VR)Ilight(V0)Idark(V0)
(1)
where Ilight is the detected photocurrent, Idark is the dark current, and V0 is the reference voltage at which no avalanche gain is observed. For our investigation, we used V0 of 1 V. At VR of 12 V, where the receiver is experimentally found to have the best BER performance, our Si APD has responsivity and avalanche gain of about 70 mA/W and 13.2, respectively, which are much smaller than the maximum values possible. Figure 3(c) shows the measured photodetection frequency response of the fabricated Si APD at VR of 12 V, which has the photodetection 3-dB bandwidth of about 5 GHz. Figure 3(c) also shows the simulated APD photodetection frequency response. For this simulation, a simplified version of the Si APD equivalent circuit model reported in [18

18. M.-J. Lee, H.-S. Kang, and W.-Y. Choi, “Equivalent circuit model for Si avalanche photodetectors fabricated in standard CMOS process,” IEEE Electron Device Lett. 29(10), 1115–1117 (2008). [CrossRef]

] is used. This equivalent circuit is very useful for OEIC receiver design since it allows simple circuit design optimization with the APD and precise design estimation of OEIC receiver bandwidth. Further details on our Si APD can be found in [16

16. J.-S. Youn, M.-J. Lee, K.-Y. Park, H. Rücker, and W.-Y. Choi, “A 12.5-Gb/s SiGe BiCMOS optical receiver with a monolithically integrated 850-nm avalanche photodetector,” in Proceedings of Optical Fiber Communication Conference (2012), paper OM3E2.

].

2.2 High-speed electronic circuits

Figure 4(a)
Fig. 4 Schematic diagrams of (a) TIA and (b) DC-balanced buffer.
shows a schematic diagram of the shunt-feedback TIA. It consists of two-stage differential voltage amplifiers and 3-kΩ feedback resistance (RF). SiGe HBTs having better high-frequency performance are used for the differential input pair, and NMOS transistors are used for the current mirror since currents can be copied without significant errors with NMOS transistors drawing negligible gate currents. The shunt-feedback TIA provides advantages of a simple structure as well as low-noise characteristics. The root mean square (rms) input-referred noise current of our TIA is about 0.73 μArms by simulation. When designing TIA, simultaneously achieving both high speed and high transimpedance is not easy when PD junction capacitance is directly coupled to TIA, which results in a dominant low-frequency pole. In our case, this problem can be alleviated as our APD has small junction capacitance, and parasitic capacitance is minimized with monolithic integration. Even with the symmetric APD configuration, differential signals at the TIA output exhibit DC offset (VDC1 ≠ VDC2) since only one APD detects optical signals. This problem is solved with a DC-balanced buffer. Figure 4(b) shows a schematic diagram of the DC-balanced buffer composed of two low-pass filters (LPFs) and fT-doubler amplifier. The low cut-off frequency of the buffer is set to 1 MHz to prevent any DC droop problem.

The black curve in Fig. 5
Fig. 5 Simulated frequency responses of the OEIC receiver front-end.
shows the simulated frequency response of the OEIC receiver front-end (APD and TIA). It has transimpedance of 68.4 dBΩ and 3-dB bandwidth of 5.2 GHz which is not sufficient for our target. The limited bandwidth is enhanced with a tunable EQ.

Figure 6(a)
Fig. 6 (a) Schematic diagrams of EQ and (b) simulated 12.5-Gb/s eye diagrams with CE = 0 fF (upper) and CE = 300 fF (lower).
shows a schematic diagram of the EQ circuit composed of a differential amplifier with emitter degeneration. Its high-frequency boosting gain can be changed by different emitter capacitance provided by a capacitor array composed of on-chip NMOS switches and metal-insulator-metal capacitors. The equivalent emitter capacitance (CE) can be discretely controlled from nominally zero to 750 fF with switches in steps of 50 fF. The effects of on-resistance of switches are carefully considered for EQ design. The enhancement in the frequency response of the OEIC receiver front-end can be observed in the simulation results of Fig. 5(b) where the receiver bandwidth can be changed from 7.5 GHz to 8.8 GHz by varying CE. Although the largest bandwidth can be achieved with CE of 750 fF, peaking in frequency response can cause signal distortion due to ringing in time domain. The optimum CE for 12.5-Gb/s operation is found to 300 fF by simulation. Figure 6(b) shows the simulated eye diagrams for the block containing APD, TIA, and EQ with CE of 0 fF and 300 fF for 12.5-Gb/s random data input. For this, current signals provided by the random bit stream module available in Cadence are applied to the APD equivalent circuit. As shown in Fig. 6(b), a clean eye diagram without any ringing can be achieved at the optimum CE of 300 fF. The LA is composed of 4-stage voltage amplifiers with each differential stage designed with resistive and capacitive degeneration. The simulated mid-band gain and 3-dB bandwidth is about 41.8 dB and 12.2 GHz, respectively. In order to compensate DC offset, on-chip LPFs are implemented with a feedback network made up of resistors and MOS capacitors. The output buffer is used for driving 50-Ω loads, necessary for measurement.

3. BER measurement results

Figure 7(a)
Fig. 7 (a) Chip photograph and (b) measurement setup.
shows the chip photograph of the fabricated OEIC receiver. The core occupies an area of 1000 μm x 280 μm. The total power consumption excluding output buffer is about 59 mW at 2.5-V supply voltage. Figure 7(b) shows the measurement setup. Measurements are done with on-wafer probing. The BER is measured using 231-1 pseudorandom bit sequence (PRBS) generated by a pulse pattern generator. An 850-nm laser diode and an external electro-optic modulator are used to generate the modulated optical signals. These signals are transmitted through 4-m long MMF and injected into the OEIC receiver using a lensed fiber. A power monitor-attenuator is used to control the Popt, measured at the lensed fiber output, some of which are reflected from the APD surface.

Figure 8(a)
Fig. 8 Measured BER performance versus (a) incident optical power (Popt), (b) equivalent emitter capacitance (CE), and (c) APD reverse bias voltage (VR). Inset shows the measured 12.5-Gb/s eye diagrams.
shows measured BER for 12.5-Gb/s optical data at different Popt. The measured optical sensitivity for BER less than 10−12 is −7 dBm for 12.5 Gb/s. The inset of Fig. 8(a) shows the measured eye diagram. For this measurement, CE of 400 fF and VR of 12 V are used. These optimum conditions are experimentally found by measuring BER performance of our OEIC receiver. This optimal value of 400 fF for CE is larger than 300 fF determined by simulation. This difference is believed due to parasitic effects that have not been accounted for by simulation as well as process variation. Figure 8(b) shows how BER changes with different values of CE. Increasing CE initially improves BER since it compensates the limited bandwidth of the APD and TIA. However, BER is degraded if CE becomes larger than 400 fF due to increased noises allowed with increased bandwidth as well as non-uniform frequency response provided by the over-equalizing EQ as can be seen in Fig. 5. The inset of Fig. 8(b) shows the measured eye diagrams with CE of 0 fF and 400 fF, respectively. Figure 8(c) shows the measured BER performance dependence on VR. BER performance is improved with increasing VR up to 12 V since the receiver signal-to-noise ratio increases with APD avalanche gain. For VR above 12 V, however, BER performance is degraded due to increased avalanche noise.

Table 1

Table 1. Performance Comparison of OEIC Receivers Fabricated with Standard Si Technology

table-icon
View This Table
shows performance comparison for our OEIC receiver with previously reported 850-nm OEIC receivers realized with standard Si technology. With high-performance Si APD and high-speed electronic circuits with equalization, our OEIC achieves the highest data rate with the smallest sensitivity. It also has the best power efficiency in mW/Gb/s.

4. Conclusion

A 12.5-Gb/s 850-nm OEIC receiver having a Si APD is realized with standard 0.25-μm SiGe BiCMOS technology for short-distance optical interconnects. The Si APD provides high responsivity and large photodetection bandwidth. The shunt-feedback TIA provides high transimpedance as well as good noise characteristics. The limited bandwidth of APD and TIA is compensated by a tunable EQ. We successfully demonstrate broadband optical data detection up to 12.5 Gb/s with BER less than 10−12 at incident optical power of −7 dBm. We believe that our SiGe BiCMOS OEIC receiver provides a promising solution for short-distance optical interconnect applications.

Acknowledgments

This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) [2012R1A2A1A01009233]. The authors are very thankful to IC Design Education Center (IDEC) for EDA software support.

References and links

1.

T.-K. Woodward and A. V. Krishnamoorthy, “1-Gb/s integrated optical detectors and receivers in commercial CMOS technologies,” IEEE J. Sel. Top. Quantum Electron. 5(2), 146–156 (1999). [CrossRef]

2.

A. C. Carusone, H. Yasotharan, and T. Kao, “CMOS technology scaling considerations for multi-gbps optical receivers with integrated photodetectors,” IEEE J. Solid-state Circuits 46(8), 1832–1842 (2011). [CrossRef]

3.

S. Radovanovic, A.-J. Annema, and B. Nauta, “A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication,” IEEE J. Solid-state Circuits 40(8), 1706–1717 (2005). [CrossRef]

4.

B. Nakhkoob, S. Ray, and M. M. Hella, “High speed photodiodes in standard nanometer scale CMOS technology: a comparative study,” Opt. Express 20(10), 11256–11270 (2012). [CrossRef] [PubMed]

5.

M. Jutzi, M. Grözing, E. Gaugler, W. Mazioschek, and M. Berroth, “2-Gb/s CMOS optical integrated receiver with a spatially modulated photodetector,” IEEE Photon. Technol. Lett. 17(6), 1268–1270 (2005). [CrossRef]

6.

W.-Z. Chen, S.-H. Huang, G.-W. Wu, C.-C. Liu, Y.-T. Huang, C.-F. Chiu, W.-H. Chang, and Y.-Z. Juang, “A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer,” in Proceedings of IEEE Asian Solid-State Circuits Conference (IEEE, 2007), pp. 396–399.

7.

F. Tavernier and M. S. J. Steyaert, “High-speed optical receivers with integrated photodiode in 130 nm CMOS,” IEEE J. Solid-state Circuits 44(10), 2856–2867 (2009). [CrossRef]

8.

T. S. Kao, F. A. Musa, and A. C. Carusone, “A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization,” IEEE Trans. Circuits Syst. I Regul. Pap. 57(11), 2844–2857 (2010). [CrossRef]

9.

D. Lee, J. Han, G. Han, and S. M. Park, “An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer,” IEEE J. Solid-state Circuits 45(12), 2861–2873 (2010). [CrossRef]

10.

S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-μm CMOS technology,” IEEE J. Solid-state Circuits 46(5), 1158–1169 (2011). [CrossRef]

11.

H.-S. Kang, M.-J. Lee, and W.-Y. Choi, “Si avalanche photodetectors fabricated in standard complementary metal-oxide-semiconductor process,” Appl. Phys. Lett. 90(15), 151118 (2007). [CrossRef]

12.

M.-J. Lee and W.-Y. Choi, “A silicon avalanche photodetector fabricated with standard CMOS technology with over 1 THz gain-bandwidth product,” Opt. Express 18(23), 24189–24194 (2010). [CrossRef] [PubMed]

13.

J.-S. Youn, M.-J. Lee, K.-Y. Park, and W.-Y. Choi, “10-Gb/s 850-nm CMOS OEIC receiver with a silicon avalanche photodetector,” IEEE J. Quantum Electron. 48(2), 229–236 (2012). [CrossRef]

14.

B. Heinemann, R. Barth, D. Knoll, H. Rücker, B. Tillack, and W. Winkler, “High-performance BiCMOS technologies without epitaxially-buried subcollectors and deep trenches,” Semicond. Sci. Technol. 22(1), 153–157 (2007). [CrossRef]

15.

D. Kucharski, D. Guckenberger, G. Masini, S. Abdalla, J. Witzens, and S. Sahni, “10Gb/s 15mW optical receiver with integrated germanium photodetector and hybrid inductor peaking in 0.13 μm SOI CMOS technology,” in Proceedings of IEEE International Solid-State Circuits Conference (IEEE, 2010), pp. 360–361.

16.

J.-S. Youn, M.-J. Lee, K.-Y. Park, H. Rücker, and W.-Y. Choi, “A 12.5-Gb/s SiGe BiCMOS optical receiver with a monolithically integrated 850-nm avalanche photodetector,” in Proceedings of Optical Fiber Communication Conference (2012), paper OM3E2.

17.

M.-J. Lee, H. Rücker, and W.-Y. Choi, “Effects of guard-ring structures on the performance of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Electron Device Lett. 33(1), 80–82 (2012). [CrossRef]

18.

M.-J. Lee, H.-S. Kang, and W.-Y. Choi, “Equivalent circuit model for Si avalanche photodetectors fabricated in standard CMOS process,” IEEE Electron Device Lett. 29(10), 1115–1117 (2008). [CrossRef]

OCIS Codes
(200.4650) Optics in computing : Optical interconnects
(250.3140) Optoelectronics : Integrated optoelectronic circuits
(250.1345) Optoelectronics : Avalanche photodiodes (APDs)

ToC Category:
Optoelectronics

History
Original Manuscript: September 18, 2012
Revised Manuscript: November 11, 2012
Manuscript Accepted: November 22, 2012
Published: December 4, 2012

Citation
Jin-Sung Youn, Myung-Jae Lee, Kang-Yeob Park, Holger Rücker, and Woo-Young Choi, "An integrated 12.5-Gb/s optoelectronic receiver with a silicon avalanche photodetector in standard SiGe BiCMOS technology," Opt. Express 20, 28153-28162 (2012)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-20-27-28153


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References

  1. T.-K. Woodward and A. V. Krishnamoorthy, “1-Gb/s integrated optical detectors and receivers in commercial CMOS technologies,” IEEE J. Sel. Top. Quantum Electron.5(2), 146–156 (1999). [CrossRef]
  2. A. C. Carusone, H. Yasotharan, and T. Kao, “CMOS technology scaling considerations for multi-gbps optical receivers with integrated photodetectors,” IEEE J. Solid-state Circuits46(8), 1832–1842 (2011). [CrossRef]
  3. S. Radovanovic, A.-J. Annema, and B. Nauta, “A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication,” IEEE J. Solid-state Circuits40(8), 1706–1717 (2005). [CrossRef]
  4. B. Nakhkoob, S. Ray, and M. M. Hella, “High speed photodiodes in standard nanometer scale CMOS technology: a comparative study,” Opt. Express20(10), 11256–11270 (2012). [CrossRef] [PubMed]
  5. M. Jutzi, M. Grözing, E. Gaugler, W. Mazioschek, and M. Berroth, “2-Gb/s CMOS optical integrated receiver with a spatially modulated photodetector,” IEEE Photon. Technol. Lett.17(6), 1268–1270 (2005). [CrossRef]
  6. W.-Z. Chen, S.-H. Huang, G.-W. Wu, C.-C. Liu, Y.-T. Huang, C.-F. Chiu, W.-H. Chang, and Y.-Z. Juang, “A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer,” in Proceedings of IEEE Asian Solid-State Circuits Conference (IEEE, 2007), pp. 396–399.
  7. F. Tavernier and M. S. J. Steyaert, “High-speed optical receivers with integrated photodiode in 130 nm CMOS,” IEEE J. Solid-state Circuits44(10), 2856–2867 (2009). [CrossRef]
  8. T. S. Kao, F. A. Musa, and A. C. Carusone, “A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization,” IEEE Trans. Circuits Syst. I Regul. Pap.57(11), 2844–2857 (2010). [CrossRef]
  9. D. Lee, J. Han, G. Han, and S. M. Park, “An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer,” IEEE J. Solid-state Circuits45(12), 2861–2873 (2010). [CrossRef]
  10. S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-μm CMOS technology,” IEEE J. Solid-state Circuits46(5), 1158–1169 (2011). [CrossRef]
  11. H.-S. Kang, M.-J. Lee, and W.-Y. Choi, “Si avalanche photodetectors fabricated in standard complementary metal-oxide-semiconductor process,” Appl. Phys. Lett.90(15), 151118 (2007). [CrossRef]
  12. M.-J. Lee and W.-Y. Choi, “A silicon avalanche photodetector fabricated with standard CMOS technology with over 1 THz gain-bandwidth product,” Opt. Express18(23), 24189–24194 (2010). [CrossRef] [PubMed]
  13. J.-S. Youn, M.-J. Lee, K.-Y. Park, and W.-Y. Choi, “10-Gb/s 850-nm CMOS OEIC receiver with a silicon avalanche photodetector,” IEEE J. Quantum Electron.48(2), 229–236 (2012). [CrossRef]
  14. B. Heinemann, R. Barth, D. Knoll, H. Rücker, B. Tillack, and W. Winkler, “High-performance BiCMOS technologies without epitaxially-buried subcollectors and deep trenches,” Semicond. Sci. Technol.22(1), 153–157 (2007). [CrossRef]
  15. D. Kucharski, D. Guckenberger, G. Masini, S. Abdalla, J. Witzens, and S. Sahni, “10Gb/s 15mW optical receiver with integrated germanium photodetector and hybrid inductor peaking in 0.13 μm SOI CMOS technology,” in Proceedings of IEEE International Solid-State Circuits Conference (IEEE, 2010), pp. 360–361.
  16. J.-S. Youn, M.-J. Lee, K.-Y. Park, H. Rücker, and W.-Y. Choi, “A 12.5-Gb/s SiGe BiCMOS optical receiver with a monolithically integrated 850-nm avalanche photodetector,” in Proceedings of Optical Fiber Communication Conference (2012), paper OM3E2.
  17. M.-J. Lee, H. Rücker, and W.-Y. Choi, “Effects of guard-ring structures on the performance of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Electron Device Lett.33(1), 80–82 (2012). [CrossRef]
  18. M.-J. Lee, H.-S. Kang, and W.-Y. Choi, “Equivalent circuit model for Si avalanche photodetectors fabricated in standard CMOS process,” IEEE Electron Device Lett.29(10), 1115–1117 (2008). [CrossRef]

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