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Optics Express

Optics Express

  • Editor: C. Martijn de Sterke
  • Vol. 20, Iss. 4 — Feb. 13, 2012
  • pp: 4331–4345
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3-D integrated heterogeneous intra-chip free-space optical interconnect

Berkehan Ciftcioglu, Rebecca Berman, Shang Wang, Jianyun Hu, Ioannis Savidis, Manish Jain, Duncan Moore, Michael Huang, Eby G. Friedman, Gary Wicks, and Hui Wu  »View Author Affiliations


Optics Express, Vol. 20, Issue 4, pp. 4331-4345 (2012)
http://dx.doi.org/10.1364/OE.20.004331


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Abstract

This paper presents the first chip-scale demonstration of an intra-chip free-space optical interconnect (FSOI) we recently proposed. This interconnect system provides point-to-point free-space optical links between any two communication nodes, and hence constructs an all-to-all intra-chip communication fabric, which can be extended for inter-chip communications as well. Unlike electrical and other waveguide-based optical interconnects, FSOI exhibits low latency, high energy efficiency, and large bandwidth density, and hence can significantly improve the performance of future many-core chips. In this paper, we evaluate the performance of the proposed FSOI interconnect, and compare it to a waveguide-based optical interconnect with wavelength division multiplexing (WDM). It shows that the FSOI system can achieve significantly lower loss and higher energy efficiency than the WDM system, even with optimistic assumptions for the latter. A 1×1-cm2 chip prototype is fabricated on a germanium substrate with integrated photodetectors. Commercial 850-nm GaAs vertical-cavity-surface-emitting-lasers (VCSELs) and fabricated fused silica microlenses are 3-D integrated on top of the substrate. At 1.4-cm distance, the measured optical transmission loss is 5 dB, the crosstalk is less than −20 dB, and the electrical-to-electrical bandwidth is 3.3 GHz. The latter is mainly limited by the 5-GHz VCSEL.

© 2012 OSA

1. Introduction

The performance of microprocessors continues to improve with technology scaling, especially through the increase of the number of cores. Communications within these chips, e.g. between processor cores and at the memory/processor interface, will demand larger bandwidth density, smaller latency and better signal integrity. To meet these demands, conventional electrical interconnects need better materials to minimize transmission loss, and increased circuit complexity (e.g. equalization) to achieve larger bandwidth, both of which increase energy consumption. Therefore, a fundamental change is required for the inter- and intra-chip interconnects. Optical interconnect exhibits inherent advantages in loss, delay and bandwidth compared to its electrical counterpart, and can potentially lead to significant performance gains and energy savings [1

1. J. W. Goodman, F. J. Leonberger, S. -Y. Kung, and R. A. Athale, “Optical interconnections for VLSI systems,” Proc. IEEE 72(7), 850–866 (1984).

, 2

2. D. A. B. Miller, “Optical interconnects to silicon,” IEEE J. Sel. Top. Quantum Electron. 6(6), 1312–1317 (2000).

]. For inter-chip communications, optical interconnects with point-to-point topologies have already been developed, typically using on-board waveguides and directly modulated lasers [3

3. L. Schares, J. A. Kash, F. E. Doany, C. L. Schow, C. Schuster, D. M. Kuchta, P. K. Pepeljugoski, J. M. Trewhella, C. W. Baks, R. A. John, L. Shan, Y. H. Kwark, R. A. Budd, P. Chiniwalla, F. R. Libsch, J. Rosner, C. K. Tsang, C. S. Patel, J. D. Schaub, R. Dangel, F. Horst, B. J. Offrein, D. Kucharski, D. Guckenberger, S. Hegde, H. Nyikal, C. -K. Lin, A. Tandon, G. R. Trott, M. Nystrom, D. P. Bour, M. R. T. Tan, and D. W. DolfiL. ScharesJ. A. KashF. E. DoanyC. L. SchowC. SchusterD. M. KuchtaP. K. PepeljugoskiJ. M. TrewhellaC. W. BaksR. A. JohnL. ShanY. H. KwarkR. A. BuddP. ChiniwallaF. R. LibschJ. RosnerC. K. TsangC. S. PatelJ. D. SchaubR. DangelF. HorstB. J. OffreinD. KucharskiD. GuckenbergerS. HegdeH. NyikalC. -K. LinA. TandonG. R. TrottM. NystromD. P. BourM. R. T. TanD. W. DolfiIBM T.J. Watson Research Center, “Terabus: terabit/second-class card-level optical interconnect technologies,” IEEE J. Sel. Top. Quantum Electron. 12(5), 1032–1044 (2006).

, 4

4. I. Young, E. Mohammed, J. Liao, A. Kern, S. Palermo, B. Block, M. Reshotko, and P. Chang, “Optical I/O technology for tera-scale computing,” IEEE Int. Solid-State Circuits Conf. 468–469 (2009).

].

For intra-chip communications, however, optical interconnect schemes previously proposed create new challenges: packet-switching optical interconnects require either all-optical switching, which is still difficult for silicon, or repeated electrooptic and optoelectronic conversions, which largely defeats optical interconnect’s advantages in latency and energy efficiency. Circuit-switching optical interconnect needs wavelength division multiplexing (WDM) to satisfy the bandwidth density requirement. WDM, however, requires precise optical filters (e.g. microrings) with accurate wavelength control and minimal transmission loss [5

5. R. G. Beausoleil, J. Ahn, N. Binkert, A. Davis, D. Fattal, M. Fiorentino, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. XuR. G. BeausoleilJ. AhnN. BinkertA. DavisD. FattalM. FiorentinoN. P. JouppiM. McLarenC. M. SantoriR. S. SchreiberS. M. SpillaneD. VantreaseQ. XuHP Labs, Palo Alto, CA, “A nanophotonic interconnect for high-performance many-core computation,” 16th IEEE Symp. High Performance Interconnects, HOTI ’08 182–189 (2008).

], which are difficult to fabricate in large-scale chips and consume significantly more power if thermal tuning is needed. In addition, all of these waveguide-based systems use an power-hungry external laser as the optical power supply, which is difficult to integrate and of high cost, especially in the WDM case.

Fig. 1 (a) Cross-sectional and (b) 3-D view of the proposed FSOI system implemented as a 3-D integrated chip stack for a multi-core microprocessor. Note that the VCSEL arrays are in the center and the photodetectors are on the periphery within each core.

2. Performance evaluation

In this paper, we expand the analysis to compare a WDM-based optical interconnect similar to the one in [5

5. R. G. Beausoleil, J. Ahn, N. Binkert, A. Davis, D. Fattal, M. Fiorentino, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. XuR. G. BeausoleilJ. AhnN. BinkertA. DavisD. FattalM. FiorentinoN. P. JouppiM. McLarenC. M. SantoriR. S. SchreiberS. M. SpillaneD. VantreaseQ. XuHP Labs, Palo Alto, CA, “A nanophotonic interconnect for high-performance many-core computation,” 16th IEEE Symp. High Performance Interconnects, HOTI ’08 182–189 (2008).

] with the proposed intra-chip FSOI system to illustrate the advantages of our approach. The operation wavelength of the WDM systems is chosen to be 1550 nm, while the FSOI system still uses 980 nm. To emphasize the effects of photonic devices and optics design, the transceiver circuits are excluded from the calculation. To simplify the calculation, the PDs in both systems are assumed to have 100% quantum efficiency and adequate bandwidth to support 10-Gbps data rate, which gives the WDM system an unfair advantage. Table 1 lists the optical and photonic device parameters for both FSOI and WDM systems.

Table 1. Photonic Device Parameters for the FSOI and WDM Optical Interconnect Systems

table-icon
View This Table

In the FSOI case, the VCSELs are based on a design demonstrated in [15

15. Y. -C. Chang and L. A. Coldren, “Optimization of VCSEL structure for high-speed operation,” IEEE 21st Int. Semiconductor Laser Conf., ISLC 159–160 (2008).

], except with In0.2Ga0.8As quantum wells and GaAs barriers. The optical transmission loss is calculated by adding an insertion loss of 0.1-dB for a microlens and 0.08-dB for a mirror. Gaussian beam clipping loss at the lenses is determined by beam divergence and lens aperture size. As the number of nodes increases, the size of the lenses are shrunk to satisfy that up to 50% of chip area is covered by microlenses, and hence optical clipping loss at the lenses increase from 0 at 4 nodes up to 47% at 64 nodes.

Fig. 2 The calculated (a) optical loss and (b) energy efficiency of the FSOI and WDM-based optical interconnect systems with respect to increasing number of nodes. The breakdown of the loss components for the WDM system is shown with dash lines. In this calculation, the transceiver electronics (laser driver and receiver) are not included in the total power consumption.

Note that the calculations are highly optimistic for the WDM system. First, it does not include the power consumption for thermal tuning, required to accurately control the wavelengths of microrings. Second, the state-of-the-art WDM laser sources have energy efficiency of a few percentage, much worse than our assumption. Finally and more importantly, silicon microring modulators exhibits insertion loss more than 0.5 dB [16

16. P. Dong, S. Liao, D. Feng, H. Liang, D. Zheng, R. Shafiiha, C. -C. Kung, W. Qian, G. Li, X. Zheng, A. V. Krishnamoorthy, and M. Asghari, “Low Vpp, ultralow-energy, compact, high-speed silicon electro-optic modulator,” Opt. Express 17(25), 22484–22490 (2009).

, 19

19. Q. Xu, S. Manipatruni, B. Schmidt, J. Shakya, and M. Lipson, “12.5 Gbit/s carrier-injection-based silicon microring silicon modulators,” Opt. Express 15(2), 430–436 (2007). [PubMed]

], resulting in over 60-dB optical loss in a single 36-node link.

3. Design of FSOI chip prototype

As shown in Fig. 3, the chip-scale prototype of the proposed intra-chip FSOI system is constructed as a 3-D chip stack. It is designed based on the following specifications and constraints: the chip has an area of 1×1 cm2, limited by the mask writer, mask size and autostepper lithography tools. The longest optical path is 1.4 cm, diagonally crossing the chip. The Ge substrate is used to build PDs and serve as a carrier for the VCSELs and microlenses. The microlenses are fabricated on a 525-μm thick fused silica substrate. The VCSELs used in the prototype is a commercial VCSEL array (Finisar V850-2092-001S, 1x4 array) with a pitch size of 250 μm, and provides 2-mW optical power at 850-nm with a 5-GHz modulation bandwidth. The pitch size between microlenses is chosen as 250-μm, matching the pitch size of the VCSEL array. To facilitate wirebonding VCSELs and PDs to the Ge carrier, a silica spacer is inserted between the microlenses and the VCSEL/PDs. A prism is used instead of micromirrors for testing convenience.

Fig. 3 Cross-sectional view of the chip-level intra-chip FSOI prototype.

3.1. Optics design

The optics design involves several device parameters: VCSEL aperture size/divergence angle, microlens aperture size and focal length, and device spacing, as shown in Fig. 4. The 850-nm VCSEL has an aperture size of 8 μm, and the full-width half-maximum (FWHM) far-field divergence angle is measured as 20° in free space at the operation bias point. Since there is a 200-μm height difference between the VCSEL chip and PD, the microlens aperture and focal length need to be adjusted correspondingly. The VCSELs and PDs are located 200-μm and 400-μm away from the back of the fused silica layer, or 565-μm and 765-μm from the lenses in air. The corresponding focal lengths are slightly less than these values because VCSELs and PDs need to be placed further away from the focal planes.

Fig. 4 Schematic of the FSOI link designed for the chip prototype. The total distance is 1.4 cm, corresponding to crossing the chip diagonally.

As discussed later in Sec. 4, microlenses are fabricated based on the photoresist melt-and-reflow technique. The desired microlens aperture size is defined by lithography, and its focal length is achieved by choosing the specific photoresist thickness. Assuming that the VCSEL is placed near the focal point of the VCSEL lens to capture more than 98% of the light, the minimal aperture size should be 200 μm. The corresponding photoresist thickness to achieve a 200-μm aperture and a 560-μm focal length lens is 10 μm. Similarly, the same photoresist thickness results in 725-μm focal length for a 220-μm aperture microlens on the PD side.

Fig. 5 Calculated beam waist size and position from the VCSEL microlens. The beam waist distance needs to be 7 mm or longer for a 1.4-cm throw distance.
Fig. 6 Calculated optical transmission (a) when the PD capture all incoming light and (b) for different PD size, with respect to relative position of the VCSEL to the focal point of its microlens. The link distance is 1.4 cm, and the light bounces twice on the 95% reflective mirrors. Note that all incoming light is captured by the PD larger than 45-μm.

Fig. 7 Calculated optical transmission (a) with respect to optical pathway at different relative distances of the VCSEL to microlens focal point and (b) for in-plane misalignment of the VCSEL source with respect to central axis of the lens at different distances.

The impact of misalignment of the VCSEL and PD with their microlenses is also examined. As shown in Fig. 7(b), when the VCSEL is misaligned to the central axis of its microlens, the optical transmission does not change for in-plane misalignments up to 6 μm at 1-cm distance. At 1.4-cm and 2-cm distance, the transmission decreases by 3 dB for a misalignment of 4.5 μm and 2.5 μm, respectively. To keep the transmission loss below 1 dB at 1.4 cm, the misalignment needs to be less than 3 μm, which is within the accuracy of typical flip-chip bonding processes.

3.2. Signaling

Fig. 8 Simulated (a) dark current with respect to bias voltage and (b) small-signal frequency response of the MSM Ge PD at 7-V bias and 850-nm illumination.

4. Device fabrication, characterization, and integration

4.1. Ge PD and carrier

Fig. 9 The fabricated 62×62-μm2 Ge MSM PD with 98-nm Si3N4 anti-reflection coating under 850-nm illumination: (a) PD structure, (b) responsivity and dark current, (c) impulse response using 50-GHz sampling oscilloscope at 7-V and 10-V bias, (d) DFT converted frequency response. The dark current density is measured as 1.7 nA/μm2 at 7-V.
Fig. 11 Images of the Ge carrier and fused silica microlens layer in the chip prototype.

Each MSM Ge PD occupies 62×62-μm2, and exhibits 83-fF capacitance, 0.315-A/W responsivity and 7-μA dark current (Fig. 9(b)), all improved from [20

20. B. Ciftcioglu, J. Zhang, R. Sobolewski, and H. Wu, “An 850-nm normal-incidence germanium metal-semiconductor-metal photodetector with 13-GHz bandwidth and 8-μA dark current,” IEEE Photon. Technol. Lett. 22(24), 1851–1853 (2010).

]. The measured dark current is larger than the simulation primarily due to accidental plasma damage at the a-Si:H layer during etching of the Si3N4 layer, increasing trap surface states at the a-Si/Si3N4 interface. This problem can be mitigated using diluted HF etching to remove Si3N4 close to the surface. The measured responsivity is less than the simulated results due to the 12% reflections from the surface caused by an 8-nm error in the anti-reflection coating thickness, and 4% scattering loss caused by the surface roughness. As shown in Figs. 9(c) and 9(d), the PD bandwidth is 9.3 GHz at a 7-V bias, mainly limited by the transit time of carriers, and wirebonds from the chip to the PCB trace.

4.2. Microlenses

Fig. 10 (a) The measured shape of the photoresist after the melt and reflow process, (b) spot sizes of collimated beams at the back surface of the 200-μm and 220-μm aperture size lenses. Based on the photoresist refractive index of 1.54 and the measured radius of curvature of 384 μm, the focal length in air is calculated as 710-μm for the 220-μm aperture lens. The peak-to-peak surface roughness is approximately 0.9 μm, corresponding to a measured 1-dB optical loss.

4.3. Chip prototype integration

The VCSEL and fabricated microlens chips need to be integrated with the Ge carrier with high horizontal accuracy and minimal tilt and rotational errors. We use non-conductive epoxy to bond the chips together and use wirebonding to electrically connect them. The tilt and rotational errors between each chip are checked under the optical interferometer and minimized before curing the epoxy. The alignment tolerance is limited to a few microns due to the 0.5-μm optical stage resolution and a maximum +/− 5-μm axial placement uncertainty of the VCSEL chip. The detailed integration steps are explained as following:

First, the 200-μm high VCSEL chip is mounted on the designated 1.45-μm deep grooves on the Ge substrate via UV-curing non-conducting epoxy. Since the grooves are etched using SF6/O2 dry-etching and coated with gold via evaporation, the surface is very smooth and flat, and does not have etch depth differences with respect to the surface of Ge carrier. Therefore, the VCSEL chip placed inside the groove has a very low tilt, which is measured as 0.15 μm and 0.27 μm along the 250-μm and 1-mm VCSEL chip width and length via an optical interferometer, respectively. After the flatness of the VCSEL chip is verified and non-conductive epoxy applied to the two sides of the chip is UV-cured, silver conducting epoxy is placed at the bottom edges of the VCSEL chip to provide a low resistance ground contact. The VCSELs and PDs are 0.75 cm apart, and VCSELs are wirebonded to the 1-mm long 50-Ω transmission lines on the Ge substrate. Each PD also has a 1-mm long feed line and a pad at the end of the line for testing. Then, a 380-μm thick fused silica spacer layer is placed on the Ge substrate and glued by UV-curing to provide a large enough gap between bondwires on the chip and the microlens layer. Finally, the fused silica chip is aligned to the Ge carrier using a high precision optical stage, and glued using non-conductive epoxy after controlling the flatness of the fused silica layer with respect to the Ge carrier via optical interferometer. The measured tilt of the microlens chip after the integration is less than 4 μm from one edge to the other. To improve the in-plane alignment of the VCSEL and microlens, the VCSELs in the array chip are turned on during the alignment process to ensure that each optical beam is centered in the middle of the microlenses. Therefore, even if the VCSEL chip is misaligned with the Ge carrier, it will be aligned well with the microlenses. This approach causes some misalignment between the microlenses and the PDs; however, the large PD area compensates for that.

5. Measurement results

In preparation for testing, the pads for the VCSELs and PDs are wirebonded to a printed circuit board (PCB) with RF connectors. This chip prototype assembly is mounted on an optical test bench with a prism which functions like two face-to-face mirrors with a 45 degree angle. Because the distance between the VCSEL chip and PDs is fixed at 0.75 cm, the prism is moved up and down to change the transmission distance.

Fig. 12 (a) Transmission and crosstalk for increasing different link distances, and (b) small-signal bandwidth at L=1-cm distance. Note that the optical transmission changes between −4 dB and −11 dB at 1 and 3.5-cm distances due to the scattering and clipping losses of the microlenses. The loss can further be alleviated by using larger NA lenses with smoother surface.

Fig. 13 (a) Simulated small-signal bandwidth of the MSM PD, commercial VCSEL and the overall link, including device parasitics, and (b) measured small-signal bandwidth using a 10-GHz VCSEL, when the PD chip is placed facing VCSEL chip without any mirrors.

6. Discussion

7. Conclusion

An intra-chip free-space optical interconnect (FSOI) system is presented. The FSOI system achieves low loss, low latency, large bandwidth and large energy efficiency for future many-core chips. A performance evaluation shows that energy efficiency of the FSOI system is significantly better than the waveguide-based WDM optical interconnects for a large number of nodes. The first 3-D integrated chip-scale prototype with a 1×1-cm2 area is designed based on real-world optical and photonic device parameters. MSM PDs are fabricated on a Ge carrier chip, and GaAs VCSELs and fused silica microlenses are 3-D integrated on the Ge carrier. The prototype achieves 4-dB optical loss, −23-dB crosstalk, and 3.3-GHz small signal bandwidth at a 1-cm transmission distance. The loss increases slightly to 5 dB with −21-dB crosstalk when the distance increases to 1.4 cm.

Acknowledgments

This work was partially supported by NSF grants CCF0829915 and DMR1124601, and the DOE Office of Inertial Confinement Fusion under Cooperative Agreement No. DE-FC52-08NA28302, the University of Rochester, and the New York State Energy Research and Development Authority. The support of DOE does not constitute an endorsement by DOE of the views expressed in this article. The authors would like to thank Cornell Nanofabrication Facility for their support.

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OCIS Codes
(130.3120) Integrated optics : Integrated optics devices
(220.0220) Optical design and fabrication : Optical design and fabrication
(250.5300) Optoelectronics : Photonic integrated circuits
(200.2605) Optics in computing : Free-space optical communication

ToC Category:
Integrated Optics

History
Original Manuscript: December 8, 2011
Revised Manuscript: January 29, 2012
Manuscript Accepted: January 30, 2012
Published: February 7, 2012

Citation
Berkehan Ciftcioglu, Rebecca Berman, Shang Wang, Jianyun Hu, Ioannis Savidis, Manish Jain, Duncan Moore, Michael Huang, Eby G. Friedman, Gary Wicks, and Hui Wu, "3-D integrated heterogeneous intra-chip free-space optical interconnect," Opt. Express 20, 4331-4345 (2012)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-20-4-4331


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References

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