OSA's Digital Library

Optics Express

Optics Express

  • Editor: C. Martijn de Sterke
  • Vol. 20, Iss. 7 — Mar. 26, 2012
  • pp: 7243–7254
« Show journal navigation

Low-loss polysilicon waveguides fabricated in an emulated high-volume electronics process

Jason S. Orcutt, Sanh D. Tang, Steve Kramer, Karan Mehta, Hanqing Li, Vladimir Stojanović, and Rajeev J. Ram  »View Author Affiliations


Optics Express, Vol. 20, Issue 7, pp. 7243-7254 (2012)
http://dx.doi.org/10.1364/OE.20.007243


View Full Text Article

Acrobat PDF (1510 KB)





Browse Journals / Lookup Meetings

Browse by Journal and Year


   


Lookup Conference Papers

Close Browse Journals / Lookup Meetings

Article Tools

Share
Citations

Abstract

We measure end-of-line polysilicon waveguide propagation losses of ~6-15 dB/cm across the telecommunication O-, E-, S-, C- and L-bands in a process representative of high-volume product integration. The lowest loss of 6.2 dB/cm is measured at 1550 nm in a polysilicon waveguide with a 120 nm x 350 nm core geometry. The reported waveguide characteristics are measured after the thermal cycling of the full CMOS electronics process that results in a 32% increase in the extracted material loss relative to the as-crystallized waveguide samples. The measured loss spectra are fit to an absorption model using defect state parameters to identify the dominant loss mechanism in the end-of-line and as-crystallized polysilicon waveguides.

© 2012 OSA

1. Introduction

Instead of relying on a separate photonic layer, several past research efforts have proposed monolithically adding photonic devices into the backend stackup of a CMOS process where the starting substrate does not affect functionality [10

10. A. M. Agarwal, L. Liao, J. S. Foresi, M. R. Black, X. Duan, and L. C. Kimerling, “Low-loss polycrystalline silicon waveguides for silicon photonics,” J. Appl. Phys. 80(11), 6120–6123 (1996). [CrossRef]

13

13. S. Kalluri, M. Ziari, A. Chen, V. Chuyanov, W. H. Steier, D. Chen, B. Jalali, H. Fetterman, and L. R. Dalton, “Monolithic integration of waveguide polymer electrooptic modulators on VLSI circuitry,” IEEE Photon. Technol. Lett. 8(5), 644–646 (1996). [CrossRef]

]. Significant technical progress has been made to fabricate photonic devices under the unique low-temperature and complex topography conditions of the electronic backend process in recent years [14

14. B. A. Block, T. R. Younkin, P. S. Davids, M. R. Reshotko, P. Chang, B. M. Polishak, S. Huang, J. Luo, and A. K. Y. Jen, “Electro-optic polymer cladding ring resonator modulators,” Opt. Express 16(22), 18326–18333 (2008), http://www.opticsinfobase.org/abstract.cfm?URI=oe-16-22-18326. [CrossRef] [PubMed]

, 15

15. G. Masini, L. Colace, and G. Assanto, “2.5 Gbit/s polycrystalline germanium-on-silicon photodetector operating from 1.3 to 1.55 µm,” Appl. Phys. Lett. 82(15), 2524–2526 (2003). [CrossRef]

]. However, backend photonic integration would add new mask steps and wafer processing to the electronic manufacturing process. This constraint is particularly severe for DRAM manufacturing. The cost sensitivity and yield constraints of the memory market limit the number of process steps and masks to the absolute minimums required. Steps that cannot be shared with existing electronic processing represent significant overall cost burdens.

To provide photonic integration with minimum impact to the overall system, front-end integration with a deposited high-index core layer is required. By integrating the photonic layer into the front-end process, all following process steps that are used to form the transistors can be leveraged to form the active and passive photonic devices. These existing steps include high-resolution lithography, low edge-roughness etching, multiple doping implants, activation annealing, silicidation, high-aspect ratio contact vias and many levels of low parasitic metal interconnect. Given this vast toolset, many active and passive photonic elements can be integrated with no increase in fabrication cost and complexity. The high thermal budget of this point of the process flow also allows for the integration of high quality photodetectors as demonstrated in recent work [16

16. S. Assefa, F. Xia, and Y. A. Vlasov, “Reinventing germanium avalanche photodetector for nanophotonic on-chip optical interconnects,” Nature 464(7285), 80–84 (2010). [CrossRef] [PubMed]

]. To maximally leverage the available processing steps, the photonic integration point studied in this work is to utilize the polysilicon transistor gate layer as the waveguide core. All contact and most implant process steps occur after the deposition of this layer. Additionally, the existing photolithography used for this layer is among the highest resolution patterning steps available within the existing electronics process. The polysilicon waveguide layer is separated from the underlying bulk-silicon wafer substrate by the oxide trench isolation used to electrically isolate transistors. The backend metal and dielectric interconnect stackup is then fabricated on top of the polysilicon waveguides.

We have previously demonstrated an example of such a platform in a bulk-CMOS process [17

17. J. S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popović, H. Li, J. Sun, T. Bonifield, R. Hollingsworth, F. X. Kärtner, H. I. Smith, V. Stojanović, and R. J. Ram, “Nanophotonic integration in state-of-the-art CMOS foundries,” Opt. Express 19(3), 2335–2346 (2011), http://www.opticsinfobase.org/abstract.cfm?URI=oe-19-3-2335. [CrossRef] [PubMed]

]. However, the mask-share, generic process model of the CMOS foundry under study in past work prevented process optimization and has limited the end-of-line polysilicon waveguide loss to ~55 dB/cm at 1550nm. In this work, we study an optimized polysilicon deposition and crystallization process to reduce the end-of-line waveguide loss. Although this platform is equally applicable to future bulk-CMOS processes, the focus of this study will be a DRAM fabrication process. DRAM products couple the process and mask design such that high-volume manufacturing processes are optimized to the specific memory product under production. The process flow of the overall DRAM product may then be optimized to include photonic-specific modifications to achieve system goals while minimizing cost and complexity. It also opens new avenues for stacked DRAM development and further improvements in communication efficiency, by enabling photonics within the stack and in each DRAM stack-layer [3

3. S. Beamer, C. Sun, Y.-J. Kwon, A. Joshi, C. Batten, V. Stojanović, and K. Asanović, “Re-architecting DRAM memory systems with monolithically integrated silicon photonics,” in International Symposium on Computer Architecture (Association for Computing Machinery, New York 2010), 129–140.

].

Recently, reports of solid phase epitaxy (SPE) silicon waveguides [18

18. H.-C. Ji, K. H. Ha, I. S. Joe, S. G. Kim, K. W. Na, D. J. Shin, S. D. Suh, Y. D. Park, and C. H. Chung, “Optical interface platform for DRAM integration,” in Optical Fiber Communication Conference, OSA Technical Digest (CD) (Optical Society of America, 2011), paper OThV4. http://www.opticsinfobase.org/abstract.cfm?URI=OFC-2011-OThV4

] and polysilicon waveguides [19

19. J. S. Orcutt, S. D. Tang, S. Kramer, H. Li, V. Stojanović, and R. J. Ram, “Low-loss polysilicon waveguides suitable for integration within a high-volume electronics process,” in Conference on Lasers and Electro-Optics, Technical Digest (CD) (Optical Society of America, 2011), paper CThHH2. http://www.opticsinfobase.org/abstract.cfm?URI=CLEO: S and I-2011-CThHH2

] have demonstrated 6.1 dB/cm and 6.2 dB/cm propagation losses respectively in DRAM integrable platforms. The recently-proposed single-crystalline SPE silicon platform requires the deposition and recrystallization of an additional front-end layer to serve as a waveguide core. In addition to the cost of the additional layer, the yield of the fabricated devices may be coupled to the heterogeneous crystallization regions formed during SPE [18

18. H.-C. Ji, K. H. Ha, I. S. Joe, S. G. Kim, K. W. Na, D. J. Shin, S. D. Suh, Y. D. Park, and C. H. Chung, “Optical interface platform for DRAM integration,” in Optical Fiber Communication Conference, OSA Technical Digest (CD) (Optical Society of America, 2011), paper OThV4. http://www.opticsinfobase.org/abstract.cfm?URI=OFC-2011-OThV4

]. Although this approach may prove to be a valuable integration platform, we instead optimize the existing polysilicon layer present in the process as the transistor gate for use as an alternate low-optical loss waveguide core. Here, we further report on the polysilicon waveguide platform that enables a high-yield, low-loss photonic platform within high-volume memory products with minimal increases in fabrication cost and complexity. The fabrication flow in a 300 mm wafer facility was designed to emulate high-volume memory integration by including the thermal cycling and full dielectric stack-up of an existing production process.

In this work, we demonstrate end-of-line 6.2 dB/cm loss at 1550 nm for a single-mode polysilicon waveguide with a 120 nm layer thickness in an electronics integration emulation process representative of a state-of-the-art DRAM product on 300 mm wafers. The emulation flow was chosen instead of the full fabrication flow to reduce cost, but all thermal cycling and wafer-level processes to produce the surrounding dielectric environment are performed to match the existing product. Since the wavelength band of operation for an integrated system is not constrained to 1550 nm, we measure waveguide propagation losses across the telecommunication O-, E-, S-, C- and L-bands (1260 nm to 1630 nm). Although the extracted bulk material absorption ranges from 4.4 cm−1 to 7.8 cm−1, confinement factor scaling enables single-mode waveguide propagation losses below 15 dB/cm across this wavelength range. By comparing the 120 nm polysilicon thickness waveguides to similarly prepared samples with a 200 nm polysilicon thickness, we estimate that despite a low top surface roughness of 0.3 nm RMS, the top surface roughness may account for up to 10% of the wide waveguide loss. To isolate the effect of the thermal processing, we compare waveguide loss from the full electronics emulation process to an as-crystallized wafer split to show that the thermal processing causes ~25% of the end-of-line polysilicon material loss. By then fitting the extracted material losses to a polysilicon absorption model based on grain-boundary defect state parameters from the literature, defect state absorption from the polysilicon is shown to be the dominant loss mechanism in both the as-crystallized and thermally processed polysilicon samples. Only transverse-electric (TE) modes are considered in this work due to the high asymmetry of the thin-core waveguides.

2. Process overview

All wafer-level processing was performed in a commercial fabrication facility on 300 mm bulk silicon wafers. The polysilicon was deposited on a 200-300 nm oxide to match the shallow trench isolation used in the memory process. After deposition and anneal of 120 nm and 200 nm thick polysilicon films on different wafers, standard 193 nm photolithography and reactive ion etching (RIE) was performed to form the waveguides. Next, the wafers were split between those that would and would not be exposed to the full memory process thermal cycling. After thermal cycling was performed on a subset of the wafers, all wafers reported here were clad with the complete, multi-layer dielectric stack-up as is used in the existing memory product. Although all dielectric layers that are within 1 µm of the polysilicon have a refractive index similar to that of fused silica, the heterogeneous electronic stack-up includes higher index layers such as silicon carbide that function as etch stops in the standard process.

Since the shallow trench isolation that formed the waveguide lower cladding was not sufficiently thick to isolate the optical mode from the substrate, die-level substrate removal was performed in an academic cleanroom for this study. This step may be obviated in an end product by increasing the thickness of the shallow trench isolation or the insertion of a deep trench isolation specifically for this purpose [18

18. H.-C. Ji, K. H. Ha, I. S. Joe, S. G. Kim, K. W. Na, D. J. Shin, S. D. Suh, Y. D. Park, and C. H. Chung, “Optical interface platform for DRAM integration,” in Optical Fiber Communication Conference, OSA Technical Digest (CD) (Optical Society of America, 2011), paper OThV4. http://www.opticsinfobase.org/abstract.cfm?URI=OFC-2011-OThV4

] to provide optical mode isolation. However, since these changes involve significant re-engineering of the front-end process, an alternative approach that would be suitable for an end system is localized substrate removal [17

17. J. S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popović, H. Li, J. Sun, T. Bonifield, R. Hollingsworth, F. X. Kärtner, H. I. Smith, V. Stojanović, and R. J. Ram, “Nanophotonic integration in state-of-the-art CMOS foundries,” Opt. Express 19(3), 2335–2346 (2011), http://www.opticsinfobase.org/abstract.cfm?URI=oe-19-3-2335. [CrossRef] [PubMed]

, 25

25. C. W. Holzwarth, J. S. Orcutt, H. Li, M. A. Popović, V. Stojanović, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized substrate removal technique enabling strong-confinement microphotonics in bulk Si CMOS processes,” in Conference on Lasers and Electro-Optics, Technical Digest (CD) (Optical Society of America, 2008), paper CThKK5. http://www.opticsinfobase.org/abstract.cfm?URI=CLEO-2008-CThKK5

, 27

27. S. Sridaran and S. A. Bhave, “Nanophotonic devices on thin buried oxide Silicon-On-Insulator substrates,” Opt. Express 18(4), 3850–3857 (2010), http://www.opticsinfobase.org/abstract.cfm?URI=oe-18-4-3850. [CrossRef] [PubMed]

, 28

28. J. E. Cunningham, I. Shubin, X. Zheng, T. Pinguet, A. Mekis, Y. Luo, H. Thacker, G. Li, J. Yao, K. Raj, and A. V. Krishnamoorthy, “Highly-efficient thermally-tuned resonant optical filters,” Opt. Express 18(18), 19055–19063 (2010), http://www.opticsinfobase.org/abstract.cfm?URI=oe-18-18-19055. [CrossRef] [PubMed]

]. In this work, blanket substrate removal was performed to minimize sample preparation complexity. To do this, the diced sample was mounted substrate-up on a 6-inch, oxidizedsilicon wafer for thermal management using Crystalbond 509. The silicon substrate was then removed by using XeF2 in a pulse-etch process. Etch cycles of 10 s interleaved by 50 s pump cycles to remove reaction products were repeated until the substrate was removed as monitored under an optical microscope. The high selectivity of silicon to oxide of the XeF2 etchant enables cm-scale die to be processed without consuming a measureable fraction of the shallow trench isolation etch stop. The final cross section and resulting waveguide modes are shown in Fig. 1
Fig. 1 (a) Cartoon cross-section of the memory process used for this work. All unlabeled dielectric layers in the immediate proximity of the waveguide core have a refractive index close to that of fused silica at the wavelengths of interest. (b) Waveguide mode profile contours for a narrow waveguide at 1550 nm with 120 nm polysilicon layer thickness illustrating the asymmetry introduced by the substrate removal and low polysilicon guided power fraction. (c) High-confinement waveguide modes such as that of an 800 nm waveguide width show no observable asymmetry and clearly confine the majority of the light in the polysilicon core region.
. The substrate removal process results in an asymmetric waveguide mode due to the refractive index asymmetry as shown in Fig. 1(b).

3. Test platform and measurement results

Due to the limited availability of laser sources for this testing, reported results are restricted to the range of 1280 nm to 1630 nm. Input and output fiber coupling to the fabricated vertical coupler gratings occurs from the “back-side” of the sample where the silicon substrate has been removed during post-foundry processing. The “front-side” of the sample is mounted to the handle oxidized silicon wafer for structural support. Since the degeneracy between upwards and downwards radiation is not broken in the grating coupler design, the insertion loss is approximately equal for coupling from either side. Cleaved single-mode fibers with a mode field diameter (MFD) of 10.4 μm at 1550 nm wavelength are used for this coupling at an angle 8 degrees off from normal incidence. Input fiber TE polarization to the grating couplers is set through a paddle-based controller by minimizing the insertion loss in short waveguide test structures where the total transmission loss is dominated by the coupler insertion loss. Since the vertical grating coupler insertion loss at this incidence angle for the TM mode is greater than 30 dB per coupler, high input polarization selectivity is possible. Device-under-test (DUT) transmission loss is then measured by comparing received output power to a 10% power tap directional coupler output that is present in the input fiber path. Although only relative transmission loss measurements are used for the propagation loss calculations, the absolute transmission loss of the setup is calibrated as a function of wavelength by replacing the DUT input and output fibers with a 1 meter fiber patch cord and recording the output fiber and tap fiber received powers. For all of the measurements reported in this work, the optical power of the input fiber was maintained to be approximately 1 mW.

The second trend is the abrupt end to the loss reduction through confinement factor scaling achieved by narrowing the waveguide width for each wavelength. If this were to be attributed to sidewall scattering having a larger impact on propagation loss, a more gradual transition to increased loss would be expected [26

26. T. Barwicz and H. A. Haus, “Three-dimensional analysis of scattering losses due to sidewall roughness in microphotonic waveguides,” IEEE J. Lightwave Technol. 23(9), 2719–2732 (2005). [CrossRef]

]. Additionally, mode solving simulations verify that the effective indices of the fundamental modes of these high loss widths are above that of any dielectric layers bordering the polysilicon core such that the waveguide is not close to cutoff. There is, however, a thin, high-index silicon carbide layer that is part of the backend electronic stack-up as an etch stop layer as shown in Fig. 1(a). The effective indices of the slab waveguide modes of this layer fall in between the effective indices of the low loss and high loss waveguide widths for each wavelength as shown in Fig. 4(b)
Fig. 4 Simulated waveguide mode (a) confinement factor and (b) effective index. Confinement factor curves from (a) are multiplied by the extracted bulk loss to generate the fit curves shown in Fig. 3. Effective index curves are overlaid with the simulated 1D slab mode index for the SiC layer that is correlated with the observed loss increase across measured wavelengths.
. Although the SiC layer is ~2 µm away from the waveguide core, mode solving simulations show significant electric field overlap with the SiC layer, shown in Fig. 1(a), at the widths where the sudden loss increase is observed. Therefore phase-matched coupling between the dielectric etch stop layers and the waveguide mode may set the limit to confinement factor scaling of waveguide loss when integrated in similar electronic platforms.

To gain some insight into the source of the waveguide loss, the extracted wavelength-dependent bulk losses were compared to theoretical predictions. The material loss was calculated by accounting for electronic transitions between mid-gap states localized at grain boundaries and Bloch states in the conduction and valence bands. Assuming a constant average oscillator strength for all involved transitions between band and midgap states, the absorption coefficient calculated from Fermi’s Golden Rule can be written as a function of the valence, conduction and midgap densities of states (DOS):

α(ω)=A[dEvρv(Ev)ρg(Ev+ω)f(Ev)[1f(Ev+ω)]+dEgρg(Eg)ρc(Eg+ω)f(Eg)[1f(Eg+ω)]]

The two integrals sum transitions from the valence band states (DOSρv) to the midgap states (DOS ρg), and from the midgap states to the conduction band (DOS ρc), as diagrammed in Fig. 5(b). The Fermi distribution function, f, enforces that all considered transitions occur between filled initial and empty final states, separated by the photon energy. Unlike the valence and conduction band density of states, the midgap state density parameter represents only a functional form of the midgap state energy distribution, which is chosen to be Gaussian. The prefactor A is then the product of the total density of midgap states and the defect-to-band transition oscillator strength, and is the sole fitting parameter in the calculation. This frequency-independent parameter serves to scale only the magnitude of the curve and not its shape.

The conduction and valence band DOS used in the calculation were taken from IBM’s DAMOCLES calculations [29]. The mid-gap density of states used was matched to that deduced by Jackson et al. [30

30. W. B. Jackson, N. M. Johnson, and D. K. Biegelsen, “Density of gap states of silicon grain boundaries determined by optical absorption,” Appl. Phys. Lett. 43(2), 195–197 (1983). [CrossRef]

], who inferred that these localized gap states manifest themselves in a broad peak ~0.35 eV above the valence band edge, as shown in Fig. 5(b). They also deduced a strong valence band-tail DOS, which is observed not to play a strong role in our material and so not included in the calculation; since our material differs significantly from theirs (the observed loss is two orders of magnitude lower), the relative concentration of tail and mid-gap localized states are expected to be different, so appropriately including the band tailing would require the addition of at least one additional fitting parameter. The Fermi-level at the grain boundary edges was assumed to be pinned at the energy of maximum midgap state density.

The results of the fit, calculated as described above, to data taken in samples removed from the flow after the crystallization anneal, as well as after the full thermal processing, are shown in Fig. 5(a). The change in state density required to fit the measured absorption of the end-of-line and as-crystallized polysilicon can then be attributed to hydrogen out-gassing reducing the passivation-fraction of dangling bond states at the grain boundaries. The ~32% change in material loss is shown in reference to the measured data points in Fig. 5(c). This provides technological feedback for further waveguide loss reduction. For example, introduction of a forming gas anneal after the completion of front-end fabrication may effectively passivate the dangling bonds. At this point of the process, the maximum processing temperatures would be reduced below 500 °C due to the metal interconnect. As a result, effective passivation of dangling bonds, which have been shown to be the dominant loss source, may be introduced into the process without further hydrogen outgassing.

4. Conclusion

In this work, end-of-line polysilicon waveguides suitable for high-volume product integration have been demonstrated with propagation losses below 10 dB/cm for the first time. Low surface roughness enabled film thickness scaling below 200 nm with relatively low propagation loss increases. Characterizing the waveguide loss as a function of wavelength over a broad spectral region of technological interest enabled the dominant physical source of the loss to be identified as defect state absorption. Confinement factor scaling of the optical mode, which demonstrates the minimal effect of both top surface and line-edge roughness, enabled waveguide propagation losses of 6-15 dB/cm across this spectrum. These results have been achieved by optimizing the anneal conditions of the existing polysilicon transistor gate layer to minimize process complexity. This may enable a lower total system cost to the SPE approach that has achieved similar optical performance at 1550 nm [18

18. H.-C. Ji, K. H. Ha, I. S. Joe, S. G. Kim, K. W. Na, D. J. Shin, S. D. Suh, Y. D. Park, and C. H. Chung, “Optical interface platform for DRAM integration,” in Optical Fiber Communication Conference, OSA Technical Digest (CD) (Optical Society of America, 2011), paper OThV4. http://www.opticsinfobase.org/abstract.cfm?URI=OFC-2011-OThV4

]. By having performed this test in an emulation environment to eliminate road blocks to end product integration, it is now possible to explore next-generation memory systems that utilize this integrated photonic platform [3

3. S. Beamer, C. Sun, Y.-J. Kwon, A. Joshi, C. Batten, V. Stojanović, and K. Asanović, “Re-architecting DRAM memory systems with monolithically integrated silicon photonics,” in International Symposium on Computer Architecture (Association for Computing Machinery, New York 2010), 129–140.

].

Acknowledgements

The authors acknowledge Dr. Jagdeep Shah of DARPA for funding under contract number W911NF-10-1-0522. Karan Mehta is partially supported by a Department of Energy Science Graduate Fellowship.

References and links

1.

M. J. Kobrinski, B. A. Block, J.-F. Zheng, B. C. Barnett, E. Mohammed, M. Reshotko, F. Robertson, S. List, I. Young, and K. Cadien, “On-chip optical interconnects,” Intel Technol. J. 8, 129–141 (2004).

2.

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009). [CrossRef]

3.

S. Beamer, C. Sun, Y.-J. Kwon, A. Joshi, C. Batten, V. Stojanović, and K. Asanović, “Re-architecting DRAM memory systems with monolithically integrated silicon photonics,” in International Symposium on Computer Architecture (Association for Computing Machinery, New York 2010), 129–140.

4.

P. Dumon, W. Bogaerts, V. Wiaux, J. Wouters, S. Beckx, J. Van Campenhout, D. Taillaert, B. Luyssaert, P. Bienstman, D. Van Thourhout, and R. Baets, “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography,” IEEE Photon. Technol. Lett. 16(5), 1328–1330 (2004). [CrossRef]

5.

C. Gunn, “CMOS photonics for high-speed interconnects,” IEEE Micro 26(2), 58–66 (2006). [CrossRef]

6.

X. Zheng, J. Lexau, Y. Luo, H. Thacker, T. Pinguet, A. Mekis, G. Li, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “Ultra-low-energy all-CMOS modulator integrated with driver,” Opt. Express 18(3), 3059–3070 (2010), http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-18-3-3059. [CrossRef] [PubMed]

7.

Y. Vlasov, W. M. J. Green, and F. Xia, “High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks,” Nat. Photonics 2(4), 242–246 (2008). [CrossRef]

8.

T. Ohsawa, K. Fujita, K. Hatsuda, T. Higashi, M. Morikado, Y. Minami, T. Shino, H. Nakajima, K. Inoh, T. Hamamoto, and S. Watanabe, “An 18.5ns 128MB SOI DRAM with floating body cell,” in International Solid-State Circuits Conference (Institute of Electrical and Electronics Engineers, New York, 2005), 459–609.

9.

J. A. Kash, “Leveraging optical interconnects in future supercomputers and servers,” in Proc. IEEE Symposium on High-Performance Interconnects (Institute of Electrical and Electronics Engineers, New York 2008), 190–194.

10.

A. M. Agarwal, L. Liao, J. S. Foresi, M. R. Black, X. Duan, and L. C. Kimerling, “Low-loss polycrystalline silicon waveguides for silicon photonics,” J. Appl. Phys. 80(11), 6120–6123 (1996). [CrossRef]

11.

K. Preston, S. Manipatruni, A. Gondarenko, C. B. Poitras, and M. Lipson, “Deposited silicon high-speed integrated electro-optic modulator,” Opt. Express 17(7), 5118–5124 (2009), http://www.opticsinfobase.org/abstract.cfm?URI=oe-17-7-5118. [CrossRef] [PubMed]

12.

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid-state Circuits 45(1), 235–248 (2010). [CrossRef]

13.

S. Kalluri, M. Ziari, A. Chen, V. Chuyanov, W. H. Steier, D. Chen, B. Jalali, H. Fetterman, and L. R. Dalton, “Monolithic integration of waveguide polymer electrooptic modulators on VLSI circuitry,” IEEE Photon. Technol. Lett. 8(5), 644–646 (1996). [CrossRef]

14.

B. A. Block, T. R. Younkin, P. S. Davids, M. R. Reshotko, P. Chang, B. M. Polishak, S. Huang, J. Luo, and A. K. Y. Jen, “Electro-optic polymer cladding ring resonator modulators,” Opt. Express 16(22), 18326–18333 (2008), http://www.opticsinfobase.org/abstract.cfm?URI=oe-16-22-18326. [CrossRef] [PubMed]

15.

G. Masini, L. Colace, and G. Assanto, “2.5 Gbit/s polycrystalline germanium-on-silicon photodetector operating from 1.3 to 1.55 µm,” Appl. Phys. Lett. 82(15), 2524–2526 (2003). [CrossRef]

16.

S. Assefa, F. Xia, and Y. A. Vlasov, “Reinventing germanium avalanche photodetector for nanophotonic on-chip optical interconnects,” Nature 464(7285), 80–84 (2010). [CrossRef] [PubMed]

17.

J. S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popović, H. Li, J. Sun, T. Bonifield, R. Hollingsworth, F. X. Kärtner, H. I. Smith, V. Stojanović, and R. J. Ram, “Nanophotonic integration in state-of-the-art CMOS foundries,” Opt. Express 19(3), 2335–2346 (2011), http://www.opticsinfobase.org/abstract.cfm?URI=oe-19-3-2335. [CrossRef] [PubMed]

18.

H.-C. Ji, K. H. Ha, I. S. Joe, S. G. Kim, K. W. Na, D. J. Shin, S. D. Suh, Y. D. Park, and C. H. Chung, “Optical interface platform for DRAM integration,” in Optical Fiber Communication Conference, OSA Technical Digest (CD) (Optical Society of America, 2011), paper OThV4. http://www.opticsinfobase.org/abstract.cfm?URI=OFC-2011-OThV4

19.

J. S. Orcutt, S. D. Tang, S. Kramer, H. Li, V. Stojanović, and R. J. Ram, “Low-loss polysilicon waveguides suitable for integration within a high-volume electronics process,” in Conference on Lasers and Electro-Optics, Technical Digest (CD) (Optical Society of America, 2011), paper CThHH2. http://www.opticsinfobase.org/abstract.cfm?URI=CLEO: S and I-2011-CThHH2

20.

J. S. Foresi, M. R. Black, A. M. Agarwal, and L. C. Kimerling, “Losses in polycrystalline silicon waveguides,” Appl. Phys. Lett. 68(15), 2052–2054 (1996). [CrossRef]

21.

Q. Fang, J. F. Song, S. H. Tao, M. B. Yu, G. Q. Lo, and D. L. Kwong, “Low loss (~6.45 dB/cm) sub-micron polycrystalline silicon waveguide integrated with efficient SiON waveguide coupler,” Opt. Express 16, 6425–6432. http://www.opticsinfobase.org/abstract.cfm?URI=oe-16-9-6425

22.

L. Liao, D. R. Lim, A. M. Agarwal, X. Duan, K. K. Lee, and L. C. Kimerling, “Optical transmission losses in polycrystalline silicon strip waveguides: effects of waveguide dimensions, thermal treatment, hydrogen passivation, and wavelength,” J. Electron. Mater. 29(12), 1380–1386 (2000). [CrossRef]

23.

S. Zhu, Q. Fang, M. B. Yu, G. Q. Lo, and D. L. Kwong, “Propagation losses in undoped and n-doped polycrystalline silicon wire waveguides,” Opt. Express 17(23), 20891–20899 (2009), http://www.opticsinfobase.org/abstract.cfm?URI=oe-17-23-20891. [CrossRef] [PubMed]

24.

S. Zhu, G. Q. Lo, J. D. Ye, and D. L. Kwong, “Influence of RTA and LTA on the optical propagation loss in polycrystalline silicon wire waveguides,” IEEE Photon. Technol. Lett. 22(7), 480–482 (2010). [CrossRef]

25.

C. W. Holzwarth, J. S. Orcutt, H. Li, M. A. Popović, V. Stojanović, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized substrate removal technique enabling strong-confinement microphotonics in bulk Si CMOS processes,” in Conference on Lasers and Electro-Optics, Technical Digest (CD) (Optical Society of America, 2008), paper CThKK5. http://www.opticsinfobase.org/abstract.cfm?URI=CLEO-2008-CThKK5

26.

T. Barwicz and H. A. Haus, “Three-dimensional analysis of scattering losses due to sidewall roughness in microphotonic waveguides,” IEEE J. Lightwave Technol. 23(9), 2719–2732 (2005). [CrossRef]

27.

S. Sridaran and S. A. Bhave, “Nanophotonic devices on thin buried oxide Silicon-On-Insulator substrates,” Opt. Express 18(4), 3850–3857 (2010), http://www.opticsinfobase.org/abstract.cfm?URI=oe-18-4-3850. [CrossRef] [PubMed]

28.

J. E. Cunningham, I. Shubin, X. Zheng, T. Pinguet, A. Mekis, Y. Luo, H. Thacker, G. Li, J. Yao, K. Raj, and A. V. Krishnamoorthy, “Highly-efficient thermally-tuned resonant optical filters,” Opt. Express 18(18), 19055–19063 (2010), http://www.opticsinfobase.org/abstract.cfm?URI=oe-18-18-19055. [CrossRef] [PubMed]

29.

http://www.research.ibm.com/DAMOCLES/html_files/phys.html

30.

W. B. Jackson, N. M. Johnson, and D. K. Biegelsen, “Density of gap states of silicon grain boundaries determined by optical absorption,” Appl. Phys. Lett. 43(2), 195–197 (1983). [CrossRef]

OCIS Codes
(220.4000) Optical design and fabrication : Microstructure fabrication
(230.7370) Optical devices : Waveguides
(250.5300) Optoelectronics : Photonic integrated circuits

ToC Category:
Optical Devices

History
Original Manuscript: January 30, 2012
Revised Manuscript: March 7, 2012
Manuscript Accepted: March 12, 2012
Published: March 14, 2012

Citation
Jason S. Orcutt, Sanh D. Tang, Steve Kramer, Karan Mehta, Hanqing Li, Vladimir Stojanović, and Rajeev J. Ram, "Low-loss polysilicon waveguides fabricated in an emulated high-volume electronics process," Opt. Express 20, 7243-7254 (2012)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-20-7-7243


Sort:  Author  |  Year  |  Journal  |  Reset  

References

  1. M. J. Kobrinski, B. A. Block, J.-F. Zheng, B. C. Barnett, E. Mohammed, M. Reshotko, F. Robertson, S. List, I. Young, K. Cadien, “On-chip optical interconnects,” Intel Technol. J. 8, 129–141 (2004).
  2. D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009). [CrossRef]
  3. S. Beamer, C. Sun, Y.-J. Kwon, A. Joshi, C. Batten, V. Stojanović, and K. Asanović, “Re-architecting DRAM memory systems with monolithically integrated silicon photonics,” in International Symposium on Computer Architecture (Association for Computing Machinery, New York 2010), 129–140.
  4. P. Dumon, W. Bogaerts, V. Wiaux, J. Wouters, S. Beckx, J. Van Campenhout, D. Taillaert, B. Luyssaert, P. Bienstman, D. Van Thourhout, R. Baets, “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography,” IEEE Photon. Technol. Lett. 16(5), 1328–1330 (2004). [CrossRef]
  5. C. Gunn, “CMOS photonics for high-speed interconnects,” IEEE Micro 26(2), 58–66 (2006). [CrossRef]
  6. X. Zheng, J. Lexau, Y. Luo, H. Thacker, T. Pinguet, A. Mekis, G. Li, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. E. Cunningham, A. V. Krishnamoorthy, “Ultra-low-energy all-CMOS modulator integrated with driver,” Opt. Express 18(3), 3059–3070 (2010), http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-18-3-3059 . [CrossRef] [PubMed]
  7. Y. Vlasov, W. M. J. Green, F. Xia, “High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks,” Nat. Photonics 2(4), 242–246 (2008). [CrossRef]
  8. T. Ohsawa, K. Fujita, K. Hatsuda, T. Higashi, M. Morikado, Y. Minami, T. Shino, H. Nakajima, K. Inoh, T. Hamamoto, and S. Watanabe, “An 18.5ns 128MB SOI DRAM with floating body cell,” in International Solid-State Circuits Conference (Institute of Electrical and Electronics Engineers, New York, 2005), 459–609.
  9. J. A. Kash, “Leveraging optical interconnects in future supercomputers and servers,” in Proc. IEEE Symposium on High-Performance Interconnects (Institute of Electrical and Electronics Engineers, New York 2008), 190–194.
  10. A. M. Agarwal, L. Liao, J. S. Foresi, M. R. Black, X. Duan, L. C. Kimerling, “Low-loss polycrystalline silicon waveguides for silicon photonics,” J. Appl. Phys. 80(11), 6120–6123 (1996). [CrossRef]
  11. K. Preston, S. Manipatruni, A. Gondarenko, C. B. Poitras, M. Lipson, “Deposited silicon high-speed integrated electro-optic modulator,” Opt. Express 17(7), 5118–5124 (2009), http://www.opticsinfobase.org/abstract.cfm?URI=oe-17-7-5118 . [CrossRef] [PubMed]
  12. I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid-state Circuits 45(1), 235–248 (2010). [CrossRef]
  13. S. Kalluri, M. Ziari, A. Chen, V. Chuyanov, W. H. Steier, D. Chen, B. Jalali, H. Fetterman, L. R. Dalton, “Monolithic integration of waveguide polymer electrooptic modulators on VLSI circuitry,” IEEE Photon. Technol. Lett. 8(5), 644–646 (1996). [CrossRef]
  14. B. A. Block, T. R. Younkin, P. S. Davids, M. R. Reshotko, P. Chang, B. M. Polishak, S. Huang, J. Luo, A. K. Y. Jen, “Electro-optic polymer cladding ring resonator modulators,” Opt. Express 16(22), 18326–18333 (2008), http://www.opticsinfobase.org/abstract.cfm?URI=oe-16-22-18326 . [CrossRef] [PubMed]
  15. G. Masini, L. Colace, G. Assanto, “2.5 Gbit/s polycrystalline germanium-on-silicon photodetector operating from 1.3 to 1.55 µm,” Appl. Phys. Lett. 82(15), 2524–2526 (2003). [CrossRef]
  16. S. Assefa, F. Xia, Y. A. Vlasov, “Reinventing germanium avalanche photodetector for nanophotonic on-chip optical interconnects,” Nature 464(7285), 80–84 (2010). [CrossRef] [PubMed]
  17. J. S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popović, H. Li, J. Sun, T. Bonifield, R. Hollingsworth, F. X. Kärtner, H. I. Smith, V. Stojanović, R. J. Ram, “Nanophotonic integration in state-of-the-art CMOS foundries,” Opt. Express 19(3), 2335–2346 (2011), http://www.opticsinfobase.org/abstract.cfm?URI=oe-19-3-2335 . [CrossRef] [PubMed]
  18. H.-C. Ji, K. H. Ha, I. S. Joe, S. G. Kim, K. W. Na, D. J. Shin, S. D. Suh, Y. D. Park, and C. H. Chung, “Optical interface platform for DRAM integration,” in Optical Fiber Communication Conference, OSA Technical Digest (CD) (Optical Society of America, 2011), paper OThV4. http://www.opticsinfobase.org/abstract.cfm?URI=OFC-2011-OThV4
  19. J. S. Orcutt, S. D. Tang, S. Kramer, H. Li, V. Stojanović, and R. J. Ram, “Low-loss polysilicon waveguides suitable for integration within a high-volume electronics process,” in Conference on Lasers and Electro-Optics, Technical Digest (CD) (Optical Society of America, 2011), paper CThHH2. http://www.opticsinfobase.org/abstract.cfm?URI=CLEO : S and I-2011-CThHH2
  20. J. S. Foresi, M. R. Black, A. M. Agarwal, L. C. Kimerling, “Losses in polycrystalline silicon waveguides,” Appl. Phys. Lett. 68(15), 2052–2054 (1996). [CrossRef]
  21. Q. Fang, J. F. Song, S. H. Tao, M. B. Yu, G. Q. Lo, and D. L. Kwong, “Low loss (~6.45 dB/cm) sub-micron polycrystalline silicon waveguide integrated with efficient SiON waveguide coupler,” Opt. Express 16, 6425–6432. http://www.opticsinfobase.org/abstract.cfm?URI=oe-16-9-6425
  22. L. Liao, D. R. Lim, A. M. Agarwal, X. Duan, K. K. Lee, L. C. Kimerling, “Optical transmission losses in polycrystalline silicon strip waveguides: effects of waveguide dimensions, thermal treatment, hydrogen passivation, and wavelength,” J. Electron. Mater. 29(12), 1380–1386 (2000). [CrossRef]
  23. S. Zhu, Q. Fang, M. B. Yu, G. Q. Lo, D. L. Kwong, “Propagation losses in undoped and n-doped polycrystalline silicon wire waveguides,” Opt. Express 17(23), 20891–20899 (2009), http://www.opticsinfobase.org/abstract.cfm?URI=oe-17-23-20891 . [CrossRef] [PubMed]
  24. S. Zhu, G. Q. Lo, J. D. Ye, D. L. Kwong, “Influence of RTA and LTA on the optical propagation loss in polycrystalline silicon wire waveguides,” IEEE Photon. Technol. Lett. 22(7), 480–482 (2010). [CrossRef]
  25. C. W. Holzwarth, J. S. Orcutt, H. Li, M. A. Popović, V. Stojanović, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized substrate removal technique enabling strong-confinement microphotonics in bulk Si CMOS processes,” in Conference on Lasers and Electro-Optics, Technical Digest (CD) (Optical Society of America, 2008), paper CThKK5. http://www.opticsinfobase.org/abstract.cfm?URI=CLEO-2008-CThKK5
  26. T. Barwicz, H. A. Haus, “Three-dimensional analysis of scattering losses due to sidewall roughness in microphotonic waveguides,” IEEE J. Lightwave Technol. 23(9), 2719–2732 (2005). [CrossRef]
  27. S. Sridaran, S. A. Bhave, “Nanophotonic devices on thin buried oxide Silicon-On-Insulator substrates,” Opt. Express 18(4), 3850–3857 (2010), http://www.opticsinfobase.org/abstract.cfm?URI=oe-18-4-3850 . [CrossRef] [PubMed]
  28. J. E. Cunningham, I. Shubin, X. Zheng, T. Pinguet, A. Mekis, Y. Luo, H. Thacker, G. Li, J. Yao, K. Raj, A. V. Krishnamoorthy, “Highly-efficient thermally-tuned resonant optical filters,” Opt. Express 18(18), 19055–19063 (2010), http://www.opticsinfobase.org/abstract.cfm?URI=oe-18-18-19055 . [CrossRef] [PubMed]
  29. http://www.research.ibm.com/DAMOCLES/html_files/phys.html
  30. W. B. Jackson, N. M. Johnson, D. K. Biegelsen, “Density of gap states of silicon grain boundaries determined by optical absorption,” Appl. Phys. Lett. 43(2), 195–197 (1983). [CrossRef]

Cited By

Alert me when this paper is cited

OSA is able to provide readers links to articles that cite this paper by participating in CrossRef's Cited-By Linking service. CrossRef includes content from more than 3000 publishers and societies. In addition to listing OSA journal articles that cite this paper, citing articles from other participating publishers will also be listed.


« Previous Article  |  Next Article »

OSA is a member of CrossRef.

CrossCheck Deposited