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Optics Express

Optics Express

  • Editor: Andrew M. Weiner
  • Vol. 21, Iss. 16 — Aug. 12, 2013
  • pp: 18884–18898
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Infrared differential interference contrast microscopy for 3D interconnect overlay metrology

Yi-sha Ku, Deh-Ming Shyu, Yeou-Sung Lin, and Chia-Hung Cho  »View Author Affiliations


Optics Express, Vol. 21, Issue 16, pp. 18884-18898 (2013)
http://dx.doi.org/10.1364/OE.21.018884


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Abstract

One of the main challenges for 3D interconnect metrology of bonded wafers is measuring through opaque silicon wafers using conventional optical microscopy. We demonstrate here the use infrared microscopy, enhanced by implementing the differential interference contrast (DIC) technique, to measure the wafer bonding overlay. A pair of two dimensional symmetric overlay marks were processed at both the front and back sides of thinned wafers to evaluate the bonding overlay. A self-developed analysis algorithm and theoretical fitting model was used to map the overlay error between the bonded wafers and the interconnect structures. The measurement accuracy was found to be better than 1.0 micron.

© 2013 OSA

Introduction

The 2011 International Technology Roadmap for Semiconductors (ITRS) expanded on the new urgency for Metrology of 3D Interconnects to include wafer alignment, interface bonding, and through silicon vias (TSVs) [1

1. ITRS Metrology2011.

]. To enable wafer scale 3D integration, the wafers require alignment of their respective patterns during the bonding step. Wafer-level alignment is fundamentally different from the stepper-based lithographic alignment typically used today in CMOS fabrication because the alignment must be performed over the entire wafer, as opposed to on a die-by-die basis. This requirement makes the overlay control much more difficult than in die-level schemes and non-idealities, such as wafer warpage and thermal expansion might lead to overlay errors. In addition, the transparency or opacity of the bonding wafers and the interface adhesive layer can also affect the wafer alignment. Wafers for 3D integration typically have existing patterns on the bonding surfaces, and the surface topography certainly make wafer to wafer bonding much more difficult than for blanket wafers. An adhesive layer is necessary when bonding two wafers in wafer-level alignment and packaging, and the thermal budget restriction on the bonding process can be quite severe. Typically the bonding process needs to be performed at temperatures less than 400°C due to the fact that CMOS circuits (usually with BEOL metallization) already exist on the wafers [2

2. S. E. Steen, D. LaTulipe, A. W. Topol, D. J. Frank, K. Belote, and D. Posillico, “Overlay as the key to drive wafer scale 3D integration,” Microelectron. Eng. 84(5-8), 1412–1415 (2007). [CrossRef]

, 3

3. R. Yu, “High density 3D integration,” IBM Research Report, Electrical Engineering RC 24516 (W0806–114), June 26 (2008).

].

Various bonding processes have been developed and applied to specific products. Wafers can be bonded face to face (F2F) or face to back (F2B), where the choice of stacking direction is dictated by how the stacks are carried in the process and what the required functionality is. For example, memory stacks tend to use F2B stacking to enable a better managed design; and memory-logic prefers F2F stacking in order to achieve a better managed registration and performance [4

4. A. Papaniko, D. Soudris, and R. Radojcic, Three Dimensional System Integration, Chapter 9 (Springer Science + Business Media LLC, 2011).

6

6. Y. Xie, J. Cong, and S. Sapatnekar, Three-Dimensional Integrated Circuit Design, Chapter 8 (Springer Science + Business Media, LLC 2010).

]. F2F alignment is the most accurate alignment available and is completely viable as a commercial process. Advanced wafer to wafer align-and-bond systems today can typically achieve tolerances in the 1 to 2 μm range. For advanced F2B schemes, typical thicknesses of the top wafer are on the order of 25–50 μm, and the bonding accuracy is highly sensitive to the bonding processes, temperature, and materials. The bonding processes cover the bonding of the carrier substrate and flipping it and removing the bulk silicon so that the back-side of the device is available for further processing. The main challenge of back-side processing after wafer bonding is concerned with perfecting the overlay: a challenge that directly affects the device performance [7

7. L. Marinier, W. van Noort, R. Pellens, B. Sutedja, R. Dekker, and H. van Zeijl, “Front- to back-side overlay optimization after wafer bonding for 3D integration,” Microelectron. Eng. 83(4–9), 1229–1232 (2006). [CrossRef]

].

The infrared microscope has proven itself to be a valuable tool for imaging through silicon when aligning the bonding wafers and characterizing voids [8

8. A. Trigg, “Applications of Infrared Microscopy to IC and MEMS Packaging,” IEEE Trans. Electron. Packag. Manuf. 26(3), 232–238 (2003). [CrossRef]

]. It offers higher spatial resolution than scanning acoustic microscopy (SAM), and is essentially nondestructive [9

9. J. Lu, A. D. Trigg, J. Wu, and T. C. Chai, “Detecting underfill delamination and cracks in flip chip on board assemblies using infrared microscope,” Int. J. Microcircuits Electron. Packag. 21(3), 231–235 (1998).

]. Current commercial infrared bright-field tools use the single image technique for F2F bonding overlay measurements because the depth of focus is sufficient enough to include both surfaces; the multiple image technique is used for F2B overlay measurements as the depth of focus is no longer sufficient to include both stacked wafer surfaces [10

10. A. C. Rudack, L. W. Kong, and G. G. Baker, “Infrared Microscopy for Overlay and Defect Metrology on 3D-Interconnect Bonded Wafers,” Advanced Semiconductor Manufacturing Conference (ASMC), IEEE/SEMI, 347–352 (2010). [CrossRef]

]. There is a need to specify the Z coordinate, or stacking wafer number through the silicon, when visiting measurement wafer sites. Two images with separate Z locations acquired by focusing on overlay marks located at each wafer surface. However, different types of inaccuracy may be introduced in doing so. Dual focusing may result in a few nanometers of X and Y translation of every micron of movement in Z. Thus a possible measurement error in a submicron range could be introduced from dual focusing the wafer surfaces of 50 μm thickness. Also defocus may change the impact of asymmetry in the imaging system on the measurement error [11

11. A. C. Diebold, Handbook of Silicon Semiconductor Metrology (CRC Press, 2001), p. 435.

].

This paper presents a novel overlay measurement technique that uses the reflection-type infrared DIC microscopy technique to measure the F2B wafer overlay by single shot image analysis. When compared to the typical configurations employed in bright-field light microscopy, the critical instrument parameters for DIC require a birefringent Nomarski prism, and the objective lens serves as both the condenser and image-forming optical system, as shown in Fig. 1
Fig. 1 Schematic of the reflection-type infrared differential interference contrast (DIC) microscope.
. A Nomarski prism is a modification of the Wollaston prism that is used in differential interference contrast microscopy. The Nomarski modification causes the light rays to come to a focal point outside the body of the prism as shown in Fig. 1, and allows greater flexibility so that when setting up the microscope the prism can be actively focused [16

16. R. D. Allen, G. B. David, and G. Nomarski, “The zeiss-Nomarski differential interference equipment for transmitted-light microscopy,” Z. Wiss. Mikrosk. 69(4), 193–221 (1969). [PubMed]

]. Because of the dual role played by the microscope objective, a Nomarski prism interference pattern projected onto the objective rear focal plane is simultaneously positioned at the focal plane of the condenser illuminating lens system. This technique works on the principle of interferometry to gain information of the optical path length difference from the step height of the overlay mark edge at both the front- and back-side wafer surfaces. This information is then used to enhance the image contrast of overlay mark features, even when located in different Z planes. Two dimensional mirror-symmetric overlay marks for both the front-side and back-side processing wafers were designed and printed on each die in order to realize the best achievable wafer to wafer bonding alignment. A self-developed analysis algorithm was used to identify the overlay error between the bonded wafers and the interconnect structures. The resultant overlay analysis map and theoretical model fitting will be presented in this paper.

2. Samples and instrumentation

2.1 Wafer processing

Figures 2(a)
Fig. 2 Process flow used to test the overlay of the front- and back-side wafer bonds.
-2(d) briefly demonstrates our bonding wafer overlay test procedure. It covers the processing of the front-side device and overlay marks (Fig. 2(a)); flipping the wafer and bonding of the carrier wafer (Fig. 2(b)); removing the bulk silicon (Fig. 2(c)); and finally processing of the back-side of the device, including overlay mark printing (Fig. 2(d)). The adhesive thickness was about 50 μm, which is fully capable of compensating for wafer topography. The bonding temperature control of the adhesive was around 300° C. The silicon wafer was ground and thinned down to 50 μm. Other passivation oxide layers with a redistribution layout and overlay marks were further processed on the back-side wafer.

2.2 Overlay target design

The two dimensional symmetric target used for the wafer overlay test is shown in Fig. 3
Fig. 3 (a) Front-side overlay marks b) Back-side overlay marks (c) Infrared bright-field images taken from wafer front-side and back-side separately.
. The feature size parameters are listed in Table 1

Table 1. Results of the wafer bonding overlay analysis.

table-icon
View This Table
. A pair of cross marks with different outer sizes (S1, S2), and arm widths (W1, W2), were printed on the front-side surface, as shown in the schematic of Fig. 3(a). Another pair of cross marks with the same design parameters but inversed printing positions (for alignment purposes) were printed on the back-side surface, as shown in Fig. 3(b). The vertical depth between the front-side and back-side marks (of the order of 50 μm) influences the behavior of the image contrast. Figure 3(c) shows one example of the images of marks acquired at the front-side and back-side focus positions, as imaged by a conventional infrared bright-field microscopy tool. Note that the depth of focus is not sufficient to include both sides of the wafer surfaces, thus the through focus technique is used to capture clear images of the front- and back-side marks separately [17

17. Y. S. Ku, A. S. Liu, and N. P. Smith, “Through-focus technique for grating linewidth analysis with nanometer sensitivity,” Opt. Eng. 45(12), 123602 (2006). [CrossRef]

, 18

18. Y. S. Ku, A. S. Liu, and N. P. Smith, “Through-Focus Technique for nano-scale grating pitch and linewidth analysis,” Opt. Express 13(18), 6699–6708 (2005). [CrossRef] [PubMed]

]. The image of the wafer back-side mark (which is directly facing up to the CCD camera), is bright and clear; the front-side mark image is somewhat darker and noisier because the passivation layers and thinned silicon wafer attenuate the infrared beam. Thus the back-side and front-side mark images are further processed to achieve similar brightness and noise levels before being merged for overlay measurements.

The printed die size was 32 x 32 mm across a 300 mm wafer. There were four quadrants in each die and the test patterns were repeated in the third quadrant (of each die), as shown in Fig. 4
Fig. 4 The layout of the 12-inch bonding overlay test wafer. Each printed die size was 32 x 32 mm. There were four quadrants for each die and the test patterns were repeated in the third quadrant of each die.
. For this work, the center position of the wafer was taken as the zero coordinate for both the X- and Y-axes.

2.3 The DIC microscope configuration

A schematic of our reflection-type DIC microscope system is shown in Fig. 1. The wavelength of the infrared light source ranged from 900 nm to 1800 nm. Illumination generated by the light source passes through the aperture and lens (lens 1 and lens 2) before encountering a linear polarizer positioned with the transmission axis oriented 90-degree with respect to the microscope frame. Linearly polarized light exiting the polarizer is reflected from the surface of a half-mirror placed at a 45-degree angle to the incident beam. The reflected light waves (which are now traveling along the microscope optical axis), enter a Nomarski prism housed above the objective in the microscope nosepiece, where they are separated into polarized orthogonal components and sheared according to the geometry of the birefringent prism. The Nomarski prism, inserted between the beam splitter and the back focal plane, separates the single polarization direction of the incident light in the XY plane: E light (extraordinary ray), and O light (ordinary ray) incident through the objective lens to the target. The microscope objective focuses the sheared orthogonal wavefronts produced by the Nomarski prism onto the surfaces of two stacked wafers. Reflected wavefronts that experience varying optical path differences as a function of the measuring marks’ surface topography, are gathered by the objective and focused onto the interference plane of the Nomarski prism where they are recombined to eliminate shearing. After exiting the Nomarski prism, the wavefronts pass through the half-mirror on a straight, and then encounter the analyzer (a second polarizer) positioned with the transmission axis oriented in a North–south direction. Lens 3 is parallel to the analyzer transmission vector and subsequently undergoes interference from the DIC image.

3. The theoretical model and measurement algorithm

3.1 Theoretical model of the reflectance DIC image

The amplitude and phase of the two spots after reflection off of the overlay target can be written as:
R1=R0expiϕ1R2=R0expi(ϕNP+ϕ2)
(1)
where R0 is the amplitude reflection coefficient, which is same for the two spots incident on the same oxide material surface; ϕ1 and ϕ2 are the phases of the two spots; and the ϕNP term is a constant phase delay that may be introduced by the Nomarski prism. In our DIC microscope’s operation mode, the phase image is intentionally emphasized and the average reflectivity image is eliminated by using a prism with ϕNP = 0. The light travels back through the optical system until it reaches the analyzer where the two polarizations are added to give a resultant amplitude, Rt, where Rt = (R1 cosq1 + R2 cosq2), and cosq1, cosq1 are derived from the angles between the polarization direction of the spots and the analyzer. After passing through the analyzer, the sum, Rt, is squared at the detector, thus producing a signal whose intensity is given by:
I=R02cos2θ1+R02cos2θ2+2R02cosθ1cosθ2cosΔϕ
(2)
Equation (2) has been simplified by the substitution Δϕ = ϕ2 - ϕ1, where Δϕ is the optical phase difference between the two spots. Typically the analyzer is oriented perpendicular to the illumination polarization. In this case, q1 = 45°, q2 = 135°, and Eq. (2) reduces to:

I=R02(1cosΔϕ)
(3)

Figure 6
Fig. 6 DIC image of (a) the back-side and (b) the front-side overlay mark in focus.
shows the in-focus images of the back-side and front-side targets captured by our self-developed DIC microscope. On the smooth and flat portions of the sample Δϕ = 0 and I = 0. A dark background is seen for the majority of the sample area as its average reflectivity is eliminated. Figure 6(a) shows the in-focus back-side overlay mark image where bright edges appear on a dark background because there is a small relative phase difference (Δϕ ≠ 0, I ≠ 0) of the two closely spaced spots whilst scanning over the shallow drop edge. Out-of-focus optical path difference changes from the front-side overlay mark are blurred and have a shallow spatial gradient in the focal plane, therefore they do not contribute much to the contrast of the image. However, Fig. 6(b) shows the in-focus front-side overlay mark image, which contains information from both the in-focus and out-of-focus planes (back-side mark plane). The front-side mark appears as bright outer cross edges. The out-of-focus optical path differences from the back-side mark are observed as a smaller bright cross with a double lined edge, peaks in the intensity distribution and a distinct dip between them. The dip feature is recognized as the edge of the back-side mark. Thus the DIC technique effectively displays the gradient of optical paths for both front- and back-side wafers; a feature that could be useful for bonding overlay studies utilizing a one shot image process.

3.2 Bonding overlay measurement algorithm

Since the overlay measurement target is two dimensionally symmetric, it should be the same at equal distances either side of its center. The overlay analysis algorithm is an adaptation of the well-known “correlation” method and is based on the edge-match symmetric centerline computation [20

20. W. D. Hopewell, R. R. Jackson, J. C. Shaw, and T. G. V. Kessel, “Latent-image control of lithography tools,” US patent 5,124,927 (1992).

]. The overlay measurement can be obtained using all possible sets of edges for both the inner and outer marks. Different edge pairs were measured separately and the results averaged together, as shown in Figs. 7(c) and 7(d). The results of these tests were combined to choose a possible center position for the marks in the image (for both inner and outer marks at the same time). The overlay error ΔX, ΔY, can then be obtained by the subtraction of the coordinate values of the center position of both the inner and outer marks in the X and Y axis, respectively.

In order to estimate the impact of tool asymmetry on measurement error, overlay measurement were made at 0 and 180 deg orientation with respect to the tool. A discrepancy in these two measurements (OL, OL180°) is called tool-induced shift (TIS).
TIS=OL0oOL180o2
(4)
We estimate TIS error of every die and remove this error from the overlay measurement. Here we use a TIS-corrected overlay estimate as an average of the measurements made at 0 and 180 deg orientation with respect to the tool:

TIScorrectedOL=OL0o+OL180o2
(5)

4. Results and discussions

Figure 8
Fig. 8 Comparison of (a) the bright-field image, (b) the dark-field image, and (c) the DIC image of the upper and lower wafer surface focus positions.
shows the results of the bonding overlay measurement of the designed mark (Fig. 3) taken using infrared bright-field, infrared dark-field and the DIC microscope with a 20X objective lens. Note that sharp images were only produced for objects in focus; out of focus objects were blurred. For the F2B wafer alignment process, there is a 50 μm depth difference between the upper pattern layer and the lower pattern layer. Usually only a very thin layer of the specimen is in focus at any level (due to the depth of focus). Thus bright-field tools use multiple imaging techniques for F2B overlay measurements as the depth of focus is no longer sufficient to include both stacked wafer surfaces. Two of the images shown in Fig. 8(a) are of the same (X, Y) coordinates but at separate Z locations: the upper and lower wafer surface. A similar situation was observed for the dark-field microscope images: the sharpness of the image was determined by the focus position of upper or lower patterned layer, as shown in Fig. 8(b). A common technique employed for infrared microscopy is to take multiple images with bright-field and dark field microscopy are then process them to achieve similar brightness and noise levels; this is then merged for overlay analysis.

Figure 8(c) shows the overlay mark images taken using our reflection-type DIC microscope at the upper and lower layer focus positions. The boundary edge of the overlay mark in the lower layer is sharp and clear, shown as an outer cross frame while it was taken into the focus position. There were double lined edge boundaries with a slight lateral shift that correspond to the out of focus image of the overlay mark from the upper layer. It is clear that the upper layer image is as sharp as the inner dual edge cross frame. The characteristic double edged appearance is a manifestation of the out-of-focus information from the upper layer mark. The contrast of the upper mark edges depends on the phase gradient along both the X and Y directions. As the overlay mark has two dimensional symmetry, double edged images are due to the differential interference contrast of the broad and blurred intensity profile. Unlike the bright-field and dark-field images shown in the bottom side of Figs. 8(a) and 8(b), respectively, Fig. 8(c) clearly shows the lower layer focusing image (including two stacking wafer layers at a defocus depth over 50 μm).

Fifty-one dies were sampled in the wafer, as shown in Fig. 4. Three measurements were made at each location for both 0° and 180° wafer orientations. Similar data was obtained for all of the wafers measured. The resulting data was averaged together, and measurement comparisons are made here using the TIS (Tool Induced Shift) corrected data.

We report TIS data from 0 and 180 deg measurements taken by both single focus Nomarski DIC microscope as shown in Figs. 9(a)
Fig. 9 TIS data taken by single focus Nomarski DIC microscope (9(a) and 9(b)), and dual focus bright field microscope (9(c)-9(f)).
and 9(b), and dual focus bright field microscope as shown in Figs. 9(c)-9(f). Figures 9(a) and 9(b) show the TIS of Nomarski DIC microscope is small, matching is good even without TIS calibration. However, Figs. 9(c)-9(f) show the TIS of bright field microscope are relatively high, which might be caused by the lateral placement errors of the frequently moving objective in dual focusing process. Thus calibrating for the TIS error may much improve the measurement accuracy when using the bright field multiple focusing technique. Then we use qualitative vector maps to illustrate the TIS-corrected overlay as shown in Fig. 10
Fig. 10 Vector plots showing the wafer map of TIS-corrected overlay error after the wafer bonding process. Data was obtained using (a) DIC microscopy, and (b) bright-field microscopy.
; the vectors represent the resulting relative overlay errors. The overlay errors were in a range of 0 to 3.5 μm, which somewhat exceeds the bonding overlay tolerance specification of 1 μm. In order to make a comparison, the same wafer map of bonding overlay error from DIC microscopy and bright-field microscopy is shown in Figs. 10(a) and 10(b), where a statistical calculation using 3-sigma modeling has been used. Both maps show great consistency within a maximum 0.33 μm measurement discrepancy and indicated that there were wafer expansion and rotation effects during the bonding process. In Fig. 11
Fig. 11 Comparison of measuring overlay point-by-point (bright-field vs. DIC) for both X and Y.
, we compare the two ways of measuring overlay point-by-point showing vector plot of the difference and plots of bright-field vs. DIC for both X and Y.

We use a linear model to describe the interfield errors by considering the overlay error at equivalent points in each exposure field. Let (X, Y) be the coordinates of a point on the wafer corresponding to the wafer center. (The center of the wafer is the most convenient location for the origin of the coordinate system.) The overlay error in the X and Y directions, ΔX and ΔY, respectively, can be expressed as:
DX=TX+EXXRXY+eX
(6)
DY=TY+EYY+RYX+eY
(7)
where the parameters TX and TY represent translation errors in the X and Y directions, respectively, and indicate an overall shift of one die relative to the other. The factors EX and EY are scale errors that represent the errors made by the bonder in compensating for wafer expansion or contraction (scale errors are dimensionless and are usually expressed in parts-per-million (ppm)). The coefficients RX and RY are rotation factors. When RX = RY one die is rotated relative to the other, and this accounts for the sign convention. The rotations are usually expressed in radians, typically in units of microradians. There are also residual errors at every measured point, eX and eY, which do not conform to the model. The data was fitted to a linear model of the bonder behavior, using data from each of the measurement targets in turn. The results of the model fitting for all fifty-six dies are shown in Table 1.

In both the bright-field and DIC microscopy results, the residuals were slightly higher in the X-axis compared to the Y-axis. This suggests that the one-shot DIC measurement is in fact more accurate in these cases. Some overlay errors could not be detected during alignment. For example, it has been observed that wafers heat during the bonding process, causing wafer scaling errors that can arise after the wafers have been aligned. Also, the non-uniformity of the adhesive material used for bonding can cause wafer warpage that possibly relates to all parameters of the overlay model fitting.

Figure 12(a)
Fig. 12 Map of the bonding wafer warpage versus overlay.
shows the warpage measurement of the 12-inch overlay test wafer after the alignment and bonding process by using a dual channel capacitive sensor module [21

21. Y. S. Ku, P. Y. Chang, and C. Shen, “Experimental investigation of three-dimensional interconnect processing wafers,” J. Micro/Nanolith. MEMS MOEMS 11(4), 043002 (2012). [CrossRef]

]. It should be noted that the noticeable convex shape indicates a dramatic change in warpage along the X-axis; no appreciable change in warpage was observed along the Y-axis. Warpage is the difference between the maximum and minimum distances of the median surface, the calculation of which uses the entire median surface data of the wafer. The wafer warpage distribution ranged from 0 to 29 μm. Bonding overlay is highly sensitive to the shape of the substrates that are aligned. The adhesives that have been used are viscous and can therefore induce slippage between the two substrates, a problem that is aggravated by CTE (Coefficient of Thermal Expansion) mismatches of the two substrates during the bonding anneal. Large variations in wafer warpage have a direct impact on the overlay, and in turn the thermal expansion. Thus non-uniform temperatures could result in the relative overlay shift following thermal expansion and warpage. The vector plot of the wafer overlay taken from Fig. 9(a) is also shown in Fig. 12(b) for comparison. It suggests that the warpage and thermal expansion was formed before the second (back-side) alignment process. The larger warpage along the X-axis actually produced a smaller expansion component in the lateral direction, thus reducing the overlay error. Instead, smaller warpage along the Y-axis could not offset the expansion influence in the lateral direction and resulted in larger overlay errors.

A cross section SEM image taken from die site 2-2 is shown in Fig. 13
Fig. 13 The measurement validation: a cross section SEM for die site 2-2.
. This image was taken for measurement validation after the DIC microscopy experiments. Although the delamination problem might be caused by the sample cutting and preparation process as shown in the bottom part of the SEM image, the bonding overlay error was 0.99 μm, generally agreeable with our DIC microscopy result of 0.61 μm. SEM cross sections are usually done for one site at a time and due to limits of time and expense is not a convenient and precise method for bonding overlay analysis, especially when global (multiple sites) inspection is required.

6. Summary

We have demonstrated that two dimensional overlay targets patterned on both the front- and back-side of the wafer can be clearly measured and analyzed using a single focus image, even when the two targets in the layer exist at a 50 μm depth of defocus. The single focus Nomarski DIC is more accurate and with much smaller TIS compared to the slower and more laborious dual focus BF IR approach. The measured overlay in this study varied from 0 to 3.5 μm; higher than required for the bonding process overlay control.

Future improvements to the measurement uncertainty are to be expected as the measurement algorithm and image capture technology continue to improve. Improvements in the fabrication process may also lead to better results. The results presented here are therefore encouraging for the future of bonding overlay metrology. Correlation of overlay offset data to electrical yield could also provide an early indication of bonded wafer yield.

Acknowledgments

This work was supported by the MOEA (Ministry of Economic Affairs; grant no. 102-EC-17-A-01-05-0337), and the Advanced Technology Project within the ITRI. The authors would like to thank the EOL/ITRI (Electronics and Opto-Electronics Research Laboratory/ Industrial Technology Research Institute) for providing 3D interconnect processing wafers. We also would like to thank Dr. Nigel Smith at Nanometrics for useful discussion with respect to the bonding overlay model.

References and links

1.

ITRS Metrology2011.

2.

S. E. Steen, D. LaTulipe, A. W. Topol, D. J. Frank, K. Belote, and D. Posillico, “Overlay as the key to drive wafer scale 3D integration,” Microelectron. Eng. 84(5-8), 1412–1415 (2007). [CrossRef]

3.

R. Yu, “High density 3D integration,” IBM Research Report, Electrical Engineering RC 24516 (W0806–114), June 26 (2008).

4.

A. Papaniko, D. Soudris, and R. Radojcic, Three Dimensional System Integration, Chapter 9 (Springer Science + Business Media LLC, 2011).

5.

P. Garrou, C. Bower, and P. Ramm, Handbook of 3D Integration-Volume1-Technology and Applications of 3D Integrated Circuits, Chapter 12 (Wiley-VCH Verlag GmbH & Co. KGaA, 2008).

6.

Y. Xie, J. Cong, and S. Sapatnekar, Three-Dimensional Integrated Circuit Design, Chapter 8 (Springer Science + Business Media, LLC 2010).

7.

L. Marinier, W. van Noort, R. Pellens, B. Sutedja, R. Dekker, and H. van Zeijl, “Front- to back-side overlay optimization after wafer bonding for 3D integration,” Microelectron. Eng. 83(4–9), 1229–1232 (2006). [CrossRef]

8.

A. Trigg, “Applications of Infrared Microscopy to IC and MEMS Packaging,” IEEE Trans. Electron. Packag. Manuf. 26(3), 232–238 (2003). [CrossRef]

9.

J. Lu, A. D. Trigg, J. Wu, and T. C. Chai, “Detecting underfill delamination and cracks in flip chip on board assemblies using infrared microscope,” Int. J. Microcircuits Electron. Packag. 21(3), 231–235 (1998).

10.

A. C. Rudack, L. W. Kong, and G. G. Baker, “Infrared Microscopy for Overlay and Defect Metrology on 3D-Interconnect Bonded Wafers,” Advanced Semiconductor Manufacturing Conference (ASMC), IEEE/SEMI, 347–352 (2010). [CrossRef]

11.

A. C. Diebold, Handbook of Silicon Semiconductor Metrology (CRC Press, 2001), p. 435.

12.

G. Normarski, “Microinterf’erom`etre diff’erential `a ondes polaris’ees,” J. Phys. Radium 16, 9S–11S (1955).

13.

M. R. Arnison, K. G. Larkin, C. J. Sheppard, N. I. Smith, and C. J. Cogswell, “Linear phase imaging using differential interference contrast microscopy,” J. Microsc. 214, 7–12 (2003). [PubMed]

14.

M. S. Elliot and W. C. K. Poon, “Conventional optical microscopy of colloidal suspensions,” Adv. Colloid Interface Sci. 92(1-3), 133–194 (2001). [CrossRef] [PubMed]

15.

T. R. Corle and G. S. Kino, “Differential interference contrast imaging on a real time confocal scanning optical microscope,” Appl. Opt. 29(26), 3769–3774 (1990). [CrossRef] [PubMed]

16.

R. D. Allen, G. B. David, and G. Nomarski, “The zeiss-Nomarski differential interference equipment for transmitted-light microscopy,” Z. Wiss. Mikrosk. 69(4), 193–221 (1969). [PubMed]

17.

Y. S. Ku, A. S. Liu, and N. P. Smith, “Through-focus technique for grating linewidth analysis with nanometer sensitivity,” Opt. Eng. 45(12), 123602 (2006). [CrossRef]

18.

Y. S. Ku, A. S. Liu, and N. P. Smith, “Through-Focus Technique for nano-scale grating pitch and linewidth analysis,” Opt. Express 13(18), 6699–6708 (2005). [CrossRef] [PubMed]

19.

A. Starikov, D. J. Coleman, P. J. Larson, A. D. Lopata, and W. A. Muth, “Accuracy of overlay measurements: tool and mark asymmetry effects,” Opt. Eng. 31(6), 1298 (1992). [CrossRef]

20.

W. D. Hopewell, R. R. Jackson, J. C. Shaw, and T. G. V. Kessel, “Latent-image control of lithography tools,” US patent 5,124,927 (1992).

21.

Y. S. Ku, P. Y. Chang, and C. Shen, “Experimental investigation of three-dimensional interconnect processing wafers,” J. Micro/Nanolith. MEMS MOEMS 11(4), 043002 (2012). [CrossRef]

OCIS Codes
(120.3940) Instrumentation, measurement, and metrology : Metrology
(180.3170) Microscopy : Interference microscopy

ToC Category:
Microscopy

History
Original Manuscript: May 13, 2013
Revised Manuscript: July 25, 2013
Manuscript Accepted: July 26, 2013
Published: August 1, 2013

Citation
Yi-sha Ku, Deh-Ming Shyu, Yeou-Sung Lin, and Chia-Hung Cho, "Infrared differential interference contrast microscopy for 3D interconnect overlay metrology," Opt. Express 21, 18884-18898 (2013)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-21-16-18884


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References

  1. ITRS Metrology2011.
  2. S. E. Steen, D. LaTulipe, A. W. Topol, D. J. Frank, K. Belote, and D. Posillico, “Overlay as the key to drive wafer scale 3D integration,” Microelectron. Eng.84(5-8), 1412–1415 (2007). [CrossRef]
  3. R. Yu, “High density 3D integration,” IBM Research Report, Electrical Engineering RC 24516 (W0806–114), June 26 (2008).
  4. A. Papaniko, D. Soudris, and R. Radojcic, Three Dimensional System Integration, Chapter 9 (Springer Science + Business Media LLC, 2011).
  5. P. Garrou, C. Bower, and P. Ramm, Handbook of 3D Integration-Volume1-Technology and Applications of 3D Integrated Circuits, Chapter 12 (Wiley-VCH Verlag GmbH & Co. KGaA, 2008).
  6. Y. Xie, J. Cong, and S. Sapatnekar, Three-Dimensional Integrated Circuit Design, Chapter 8 (Springer Science + Business Media, LLC 2010).
  7. L. Marinier, W. van Noort, R. Pellens, B. Sutedja, R. Dekker, and H. van Zeijl, “Front- to back-side overlay optimization after wafer bonding for 3D integration,” Microelectron. Eng.83(4–9), 1229–1232 (2006). [CrossRef]
  8. A. Trigg, “Applications of Infrared Microscopy to IC and MEMS Packaging,” IEEE Trans. Electron. Packag. Manuf.26(3), 232–238 (2003). [CrossRef]
  9. J. Lu, A. D. Trigg, J. Wu, and T. C. Chai, “Detecting underfill delamination and cracks in flip chip on board assemblies using infrared microscope,” Int. J. Microcircuits Electron. Packag.21(3), 231–235 (1998).
  10. A. C. Rudack, L. W. Kong, and G. G. Baker, “Infrared Microscopy for Overlay and Defect Metrology on 3D-Interconnect Bonded Wafers,” Advanced Semiconductor Manufacturing Conference (ASMC), IEEE/SEMI, 347–352 (2010). [CrossRef]
  11. A. C. Diebold, Handbook of Silicon Semiconductor Metrology (CRC Press, 2001), p. 435.
  12. G. Normarski, “Microinterf’erom`etre diff’erential `a ondes polaris’ees,” J. Phys. Radium16, 9S–11S (1955).
  13. M. R. Arnison, K. G. Larkin, C. J. Sheppard, N. I. Smith, and C. J. Cogswell, “Linear phase imaging using differential interference contrast microscopy,” J. Microsc.214, 7–12 (2003). [PubMed]
  14. M. S. Elliot and W. C. K. Poon, “Conventional optical microscopy of colloidal suspensions,” Adv. Colloid Interface Sci.92(1-3), 133–194 (2001). [CrossRef] [PubMed]
  15. T. R. Corle and G. S. Kino, “Differential interference contrast imaging on a real time confocal scanning optical microscope,” Appl. Opt.29(26), 3769–3774 (1990). [CrossRef] [PubMed]
  16. R. D. Allen, G. B. David, and G. Nomarski, “The zeiss-Nomarski differential interference equipment for transmitted-light microscopy,” Z. Wiss. Mikrosk.69(4), 193–221 (1969). [PubMed]
  17. Y. S. Ku, A. S. Liu, and N. P. Smith, “Through-focus technique for grating linewidth analysis with nanometer sensitivity,” Opt. Eng.45(12), 123602 (2006). [CrossRef]
  18. Y. S. Ku, A. S. Liu, and N. P. Smith, “Through-Focus Technique for nano-scale grating pitch and linewidth analysis,” Opt. Express13(18), 6699–6708 (2005). [CrossRef] [PubMed]
  19. A. Starikov, D. J. Coleman, P. J. Larson, A. D. Lopata, and W. A. Muth, “Accuracy of overlay measurements: tool and mark asymmetry effects,” Opt. Eng.31(6), 1298 (1992). [CrossRef]
  20. W. D. Hopewell, R. R. Jackson, J. C. Shaw, and T. G. V. Kessel, “Latent-image control of lithography tools,” US patent 5,124,927 (1992).
  21. Y. S. Ku, P. Y. Chang, and C. Shen, “Experimental investigation of three-dimensional interconnect processing wafers,” J. Micro/Nanolith. MEMS MOEMS11(4), 043002 (2012). [CrossRef]

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