## The influence of substrate on SOI photonic crystal thermo-optic devices |

Optics Express, Vol. 21, Issue 4, pp. 4235-4243 (2013)

http://dx.doi.org/10.1364/OE.21.004235

Acrobat PDF (1318 KB)

### Abstract

We investigate the influence of the substrate on a photonic crystal thermo-optic device on a silicon-on-insulator (SOI) platform. The substrate-induced thermo-optic tuning is obtained as a function of key physical parameters, based on a semi-analytic theory that agrees well with numeric simulations. It is shown that for some devices, the substrate’s contribution to the thermo-optic tuning can exceed 10% for a heater located in the waveguide core and much higher for some other configurations. The slow response of the substrate may also significantly slow down the overall response time of the device. Strategies of minimizing the substrate’s influence are discussed.

© 2013 OSA

## 1. Introduction

1. R. A. Soref, “The past, present, and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron. **12**(6), 1678–1687 (2006). [CrossRef]

3. G. K. Celler and S. Cristoloveanu, “Frontiers of silicon-on-insulator,” J. Appl. Phys. **93**(9), 4955–4978 (2003). [CrossRef]

4. L. Gu, W. Jiang, X. Chen, and R. T. Chen, “Physical mechanism of p-i-n diode based photonic crystal silicon electrooptic modulators for gigahertz operation,” IEEE J. Sel. Top. Quantum Electron. **14**(4), 1132–1139 (2008). [CrossRef]

4. L. Gu, W. Jiang, X. Chen, and R. T. Chen, “Physical mechanism of p-i-n diode based photonic crystal silicon electrooptic modulators for gigahertz operation,” IEEE J. Sel. Top. Quantum Electron. **14**(4), 1132–1139 (2008). [CrossRef]

12. M. Chahal, G. K. Celler, Y. Jaluria, and W. Jiang, “Thermo-optic characteristics and switching power limit of slow-light photonic crystal structures on a silicon-on-insulator platform,” Opt. Express **20**(4), 4225–4231 (2012). [CrossRef] [PubMed]

8. L. Gu, W. Jiang, X. Chen, and R. T. Chen, “Thermooptically tuned photonic crystal waveguide silicon-on-insulator Mach-Zehnder interferometers,” IEEE Photon. Technol. Lett. **19**(5), 342–344 (2007). [CrossRef]

*t*) and the thickness of the buried oxide layer (

_{sub}*t*). Our results reveal some important aspects/scenarios in which the influence of the substrate can be surprisingly high and cannot be neglected in device design. As numerical simulation of a full substrate can be extremely time-consuming, we have developed a semi-analytic theory that can be used for quick assessment of the substrate effect in thermo-optic device design. Guided by this theory, strategies of minimizing the influence of the substrate will be discussed.

_{ox}## 2. Substrate temperature profile

*W*and length

*L*embedded in the core of the photonic crystal waveguide (PCW). The heat source can be constructed from a lightly doped (e.g. ~10

^{14}cm

^{−3}) Si strip surrounded by relatively highly doped (e.g. ~10

^{17}cm

^{−3}) silicon on both sides [5

5. Y. A. Vlasov, M. O’Boyle, H. F. Hamann, and S. J. McNab, “Active control of slow light on a chip with photonic crystal waveguides,” Nature **438**(7064), 65–69 (2005). [CrossRef] [PubMed]

12. M. Chahal, G. K. Celler, Y. Jaluria, and W. Jiang, “Thermo-optic characteristics and switching power limit of slow-light photonic crystal structures on a silicon-on-insulator platform,” Opt. Express **20**(4), 4225–4231 (2012). [CrossRef] [PubMed]

*κ*, which is determined by the PCW structure [12

_{eff}12. M. Chahal, G. K. Celler, Y. Jaluria, and W. Jiang, “Thermo-optic characteristics and switching power limit of slow-light photonic crystal structures on a silicon-on-insulator platform,” Opt. Express **20**(4), 4225–4231 (2012). [CrossRef] [PubMed]

*T*= 300 K to emulate a heat sink under the substrate. Because the heat dissipation from the top and side surfaces is negligible due to the small thermal conductivity and a small heat transfer coefficient in natural convection of air, adiabatic boundary conditions are used for these surfaces [6

_{0}6. M. T. Tinker and J.-B. Lee, “Thermal and optical simulation of a photonic crystal light modulator based on the thermo-optic shift of the cut-off frequency,” Opt. Express **13**(18), 7174–7188 (2005). [CrossRef] [PubMed]

**20**(4), 4225–4231 (2012). [CrossRef] [PubMed]

*κ*), silicon oxide (

_{Si}*κ*) and photonic crystal

_{ox}*κ*are from Ref. [12

_{eff}**20**(4), 4225–4231 (2012). [CrossRef] [PubMed]

*x-y*plane) of the vertical heat flux, and then utilize an electric field analogy to obtain the vertical temperature profile in the substrate. Our previous work showed that the heat flux at the top surface of the buried oxide layer has an effective width of

*W*+ 2

*X*due to lateral thermal spreading in the silicon PCW cladding, where

_{spr}*X*is given by

_{spr}*t*is the thickness of the top Si layer. As the heat flows down through the oxide layer, it also spreads laterally. With a fixed-angle heat spreading model, we can readily show that the effective width and length of the heat flux cross-section are increased by Δ

_{Si}*W*= Δ

*L*= 2

*t*tan45° after passing through the oxide layer and reaching the top surface of the substrate [15

_{ox}15. R. F. David, “Computerized thermal analysis of hybrid circuits,” IEEE Trans. Parts Hybrids Packag. **13**(3), 283–290 (1977). [CrossRef]

*z*-axis due to a finite sheet of charge uniformly distributed on the

*x-y*plane and centered at the origin is given by [17]where

*ρ*is the charge density,

_{s}*ε*is the permittivity, and

*W*and

*L*are the width and length of the sheet. It is well known that the steady state heat conduction equation resembles the static electric field equation as both are Poisson’s equations [18]. By the thermal-electrical analogy,it can readily be shown that for a similar heat source of width

*W’*and length

*L’*, the temperature profile along the

*z*-axis in a semi-infinite (

*z*>0) homogeneous medium is given bywhere

*Q*is the power of the source, and

*κ*is the thermal conductivity of the medium. Note the

*z*axis points downward and

*z*= 0 is assumed to be on the top surface of the substrate. The factor 2 is due to the semi-infinite medium (the mirror image of the half space of

*z*>0 in the other half space of

*z*<0 that will add a source at

*z*= 0

^{−}so that this half space problem corresponds to a full space problem with a source of 2

*Q*). The integration in Eq. (3) has a fairly lengthy result, where

*z*-axis are plotted in Fig. 2(a) for three different values of heat source length. Note that the temperature of the substrate bottom surface,

*T*(

*t*) =

_{sub}*T*, is used as the reference. In addition, simulations are performed for different values of

_{0}*t*, as plotted in Fig. 2(b) along with the analytic results. Evidently, the vertical temperature profiles given by semi-analytic theory agree fairly well with the FEM simulations. As could be expected, the (total) temperature rise in the substrate, Δ

_{ox}*T*≡

_{sub}*T*(0)−

*T*(

*t*), increases as

_{sub}*L*or

*t*decreases.

_{ox}## 3. Fractional thermo-optic tuning due to the substrate

*T*Δ

_{tot}=*T*Δ

_{ox}+*T*). For example, in thermo-optic tunable delay lines, the total change of the delay time in the PCW (Δ

_{sub}*τ*), which is proportional to the total temperature rise in the waveguide (for small change of refractive index Δ

_{tot}*n*<<1), is also affected by the temperature rise in the substrate. Assume Δ

*τ*=

_{tot}*μ*Δ

*T*, where

_{tot}*μ*is a constant depending on the thermo-optic coefficient of silicon. Because Δ

*τ*=

_{tot}*μ*Δ

*T*+

_{ox}*μ*Δ

*T*, we can define the substrate-induced delay tuning as Δ

_{sub}*τ*=

_{sub}*μ*Δ

*T*(note that Δ

_{sub}*τ*does not mean the time delay of light in the substrate, but the delay in the waveguide due to the substrate temperature). Note that Δ

_{sub}*T*can also be analytically expressed as [12

_{ox}**20**(4), 4225–4231 (2012). [CrossRef] [PubMed]

*f*

_{sub}= Δ

*τ*Δ

_{sub}/*τ*.

_{tot}*f*

_{sub}is less than 5%. From the plot, it is evident that as the substrate thickness increases,

*f*

_{sub}increases as expected. In Fig. 3(b), simulation and analytic results are plotted for different buried oxide layer thicknesses. As

*t*increases, Δ

_{ox}*T*decreases (and Δ

_{sub}*T*increases); consequently

_{ox}*f*

_{sub}decreases.

*n*in the range of 30~100 [12

_{g}**20**(4), 4225–4231 (2012). [CrossRef] [PubMed]

19. W. Song, R. A. Integlia, and W. Jiang, “Slow light loss due to roughness in photonic crystal waveguides: an analytic approach,” Phys. Rev. B **82**(23), 235306 (2010). [CrossRef]

*f*increases as the heater becomes longer. To explore its upper limit for very long heaters,

_{sub}*f*is calculated semi-analytically for

_{sub}*L*up to 10mm and the trend is shown in a semi-log plot in Fig. 4 .

*L*continues increasing,

*f*increases asymptotically towards a finite upper limit whose value depends on

_{sub}*t*. This upper limit occurs because for

_{ox}*L→∞*, the structure can be treated as a two-dimensional problem in the

*x-z*plane. For

*L→∞*, it is necessary to define the linear power density as

*L→∞*can be expressed as

*f*calculated with Eq. (5). Evidently, they agree very well with the results from Eq. (3) at long

_{sub}*L*. In typical SOI devices,

*t*is on the order of hundreds of microns and

_{sub}*W′*is on the order of tens of microns, thus

*t*>>

_{sub}*W’*. This can be used to further simplify Eq. (5) to

## 4. Minimizing the substrate-induced thermo-optic effect

20. M. Y. Chen, H. Subbaraman, and R. T. Chen, “Photonic crystal fiber beamformer for multiple X band phased-array antenna transmissions,” IEEE Photon. Technol. Lett. **20**(5), 375–377 (2008). [CrossRef]

*T*, Δ

_{ox}*T*, and Δ

_{sub}*T*data are extracted from a FEM simulation of the transient response of a structure. Note that Δ

_{tot}*T*and Δ

_{ox}*T*defined in this work do not refer to a uniform temperature increase in the oxide and the substrate, but the temperature difference between the upper and lower surfaces of these two regions. The rise time (10% to 90%) for Δ

_{sub}*T*is on the order of 100μs whereas the rise time (10% to 90%) for Δ

_{sub}*T*is on the order of 1μs. Note that the 10% point of these traces are all very close to

_{ox}*t*= 0 and their difference in time is very small. On the other hand, the time difference of the 90% points of the Δ

*T*and Δ

_{sub}*T*traces is very large; thus only the 90% points are marked. The fall time of each curve is on the same order as its respective rise time. The rise/fall time can be estimated from

_{ox}*ρ*is the density and

*c*the specific heat capacity of the material and

*Z*is the heat conduction length in this material [12

**20**(4), 4225–4231 (2012). [CrossRef] [PubMed]

*T*, the pertinent material is the oxide,

_{ox}*Z*is the thickness of the buried oxide layer. For Δ

*T*, the pertinent material is silicon,

_{sub}*Z*is on the order of the substrate thickness. Silicon and SiO

_{2}have comparable

*ρc*; and

*κ*is about two orders of magnitude higher than

_{Si}*κ*. The substrate thickness is usually two orders larger than the buried oxide thickness. Based on these values, the transient response of the substrate is expected to be roughly two orders of magnitude slower than the buried oxide layer. Assume an analog application requires 1% delay tuning accuracy. Then the device analyzed in Fig. 5 is considered stable only after Δ

_{ox}*T*reach ~90% of its steady-state value (so that Δ

_{sub}*T*reaches 99% of its steady-state value because this device has Δ

_{tot}*T*0.09Δ

_{sub}~*T*in the steady-state). Therefore, for this analog application, the device response time is practically ~100 μs. This is much longer than the intrinsic response time of the oxide layer.

_{tot}*f*(

_{sub}*L→∞*) varies with key physical parameters. Results are plotted in Fig. 6 for different substrate thicknesses and oxide thicknesses. It can be seen that the influence of the substrate can be reduced by increasing the thickness of the buried oxide layer. This reduction can be attributed to two trends: Δ

*T*increases as

_{ox}*t*

_{ox}^{1/2}and Δ

*T*decreases with

_{sub}*t*due to the term ln[2

_{ox}*t*(

_{sub}/*W + 2X*)] in Eq. (6) [12

_{spr}+ 2t_{ox}**20**(4), 4225–4231 (2012). [CrossRef] [PubMed]

*f*is less than 5% for all cases shown in Fig. 6. Furthermore, reducing the substrate thickness can also reduce Δ

_{sub}*T*according to Eq. (5). It can be readily shown that

_{sub}*f*varies faster than

_{sub}*t*

_{ox}^{-1/2}with respect to the oxide thickness and varies logarithmically with

*t*. Thus, mathematically,

_{sub}*f*can be more effectively reduced by increasing

_{sub}*t*.

_{ox}*t*>5μm in making high-quality SOI wafers. Second, by increasing

_{ox}*t*, the heat conductance between source and sink becomes smaller, which hampers device heat dissipation. Third, thicker oxide will lead to an increase of response time [12

_{ox}**20**(4), 4225–4231 (2012). [CrossRef] [PubMed]

22. J. A. Rogers, M. G. Lagally, and R. G. Nuzzo, “Synthesis assembly and applications of semiconductor nanomembranes,” Nature **477**(7362), 45–53 (2011). [CrossRef] [PubMed]

23. S. Huang, J. Luo, H. L. Yip, A. Ayazi, X. H. Zhou, M. Gould, A. Chen, T. Baehr-Jones, M. Hochberg, and A. K. Y. Jen, “Efficient poling of electro-optic polymers in thin films and silicon slot waveguides by detachable pyroelectric crystals,” Adv. Mater. (Deerfield Beach Fla.) **24**(10), OP42–OP47 (2012). [CrossRef] [PubMed]

*x*

_{heater}= 7μm, and the PCW core located at

*x*

_{core}= 0), then the temperature rise in the PCW core Δ

*T*could be 2~3 times smaller than the Δ

_{core}*T*at the heater due to the exponential temperature drop along

_{tot}*x*[12

**20**(4), 4225–4231 (2012). [CrossRef] [PubMed]

*f*in the PCW core. To analyze such a case, we need to consider the total temperature rise in the top Si layer Δ

_{sub}*T*, the vertical temperature difference between top and bottom surfaces of the substrate Δ

_{tot}*T*, and the vertical temperature difference in oxide Δ

_{sub}*T*in

_{ox}*two different vertical planes*at

*x*=

*x*

_{heater}and

*x*=

*x*

_{core}, respectively. Obviously, the temperature rise in the core is just Δ

*T*in the plane at

_{tot}*x*=

*x*

_{core}, Δ

*T*≡Δ

_{core}*T*(

_{tot}*x*

_{core}). The actual delay tuning is determined by Δ

*T*. Because Δ

_{core}*T*is much lower than Δ

_{core}*T*(

_{tot}*x*

_{heater}), the fractional thermal tuning in the PCW core due to the substrate in this case

*f*(

_{sub}*x*

_{core}) = Δ

*T*(

_{sub}*x*

_{core})

*/*Δ

*T*could be much larger than Δ

_{core}*T*(

_{sub}*x*)

_{heater}*/*Δ

*T*(

_{tot}*x*) given in preceding sections. In the worst case,

_{heater}*f*(

_{sub}*x*

_{core}) may exceed 20% in a non-optimal structure.

*f*(

_{sub}*x*

_{core}) will reach ~25%, as shown in Fig. 7 . Because

*f*(

_{sub}*x*

_{core}) is far above 10%, the 10%-90% rise/fall time of Δ

*T*(

_{tot}*x*

_{core}) also elongates to ~12μs (compared to ~1μs rise/fall time from 10% to 90% for Δ

*T*in Fig. 5). This can explain the long rise time observed in prior experiments where the heater is located at the PCW edge (for example Ref. [8

_{tot}8. L. Gu, W. Jiang, X. Chen, and R. T. Chen, “Thermooptically tuned photonic crystal waveguide silicon-on-insulator Mach-Zehnder interferometers,” IEEE Photon. Technol. Lett. **19**(5), 342–344 (2007). [CrossRef]

*r/a*= 025~0.35), has a relatively weak influence on

*f*, as shown in the inset of Fig. 6. The heater width

_{sub}*W*is usually recommended to be relatively small to improve the heating efficiency [12

**20**(4), 4225–4231 (2012). [CrossRef] [PubMed]

*W*<<2

*X*, and the influence of

_{spr}*W*on the Δ

*T*is fairly small according to our calculation. Also note that due to the complex anisotropic structure of a narrow heater embedded in a photonic crystal waveguide, the traditional fixed-angle spreading model is not applicable to this entire structure. The fixed-angle model can, however, be useful for a single

_{sub}*thin*layer such as the buried oxide layer. Within the top silicon layer the temperature variation is very small along

*y*and

*z*axes [12

**20**(4), 4225–4231 (2012). [CrossRef] [PubMed]

*T*between two approaches is less than 5% in all cases we have simulated. The discrepancy can be attributed to several models used in this semi-analytic theory, including the quasi-1D model for heat transfer in a SOI PCW [12

_{sub}**20**(4), 4225–4231 (2012). [CrossRef] [PubMed]

15. R. F. David, “Computerized thermal analysis of hybrid circuits,” IEEE Trans. Parts Hybrids Packag. **13**(3), 283–290 (1977). [CrossRef]

**20**(4), 4225–4231 (2012). [CrossRef] [PubMed]

*T*contributes less than ~12% of Δ

_{sub}*T*. Therefore, 5% discrepancies of Δ

_{tot}*T*contribute less than 0.6% of the discrepancies of the overall temperature Δ

_{sub}*T*. Such discrepancies of Δ

_{tot}*T*are considered very small and very difficult to further improve upon. Furthermore, it should be noted that our motivation for developing a (semi-)analytic theory to describe a phenomenon is not to achieve best accuracy, but to gain physical insight that cannot be obtained through numerical simulations, such as how Δ

_{tot}*T*scales with many key physical parameters given in an analytic expression. It would be highly challenging to obtain such scalings or trends through FEM simulations when multiple parameters are involved and some parameters are varying over a large range. For example, to obtain the asymptotic trend shown in Fig. 4 through FEM simulations, it would require a prohibitive amount of computational resources because it would be necessary to simulate many instances of extremely long/large devices with both

_{sub}*L*and

*t*varying.

_{ox}*y*-axis over that along

*x*-axis is not as large as in PCWs. It can be expected that the substrate-induced effect in such structures will resemble short PCWs, which suggests

*f*

_{sub}is typically a smaller value according to Fig. 4. It may also be interesting to extend this work to integrated circuits on a SOI wafer. Because the transistors generally have smaller dimensions along

*x*and

*y*axis, it is expected that the substrate temperature rise due to a single transistor is fairly small. For a complicated circuit including many transistors and metal interconnects in multilayer 3D configurations, it remains a challenging problem to investigate the substrate-induced thermal issues. Detailed discussion of these further research topics is beyond the scope of this work.

## 5. Conclusion

## Acknowledgments

## References and links

1. | R. A. Soref, “The past, present, and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron. |

2. | G. T. Reed, ed., |

3. | G. K. Celler and S. Cristoloveanu, “Frontiers of silicon-on-insulator,” J. Appl. Phys. |

4. | L. Gu, W. Jiang, X. Chen, and R. T. Chen, “Physical mechanism of p-i-n diode based photonic crystal silicon electrooptic modulators for gigahertz operation,” IEEE J. Sel. Top. Quantum Electron. |

5. | Y. A. Vlasov, M. O’Boyle, H. F. Hamann, and S. J. McNab, “Active control of slow light on a chip with photonic crystal waveguides,” Nature |

6. | M. T. Tinker and J.-B. Lee, “Thermal and optical simulation of a photonic crystal light modulator based on the thermo-optic shift of the cut-off frequency,” Opt. Express |

7. | T. Chu, H. Yamada, S. Ishida, and Y. Arakawa, “Thermooptic switch based on photonic-crystal line-defect waveguides,” IEEE Photon. Technol. Lett. |

8. | L. Gu, W. Jiang, X. Chen, and R. T. Chen, “Thermooptically tuned photonic crystal waveguide silicon-on-insulator Mach-Zehnder interferometers,” IEEE Photon. Technol. Lett. |

9. | D. M. Beggs, T. P. White, L. O’Faolain, and T. F. Krauss, “Ultracompact and low-power optical switch based on silicon photonic crystals,” Opt. Lett. |

10. | N. Ishikura, T. Baba, E. Kuramochi, and M. Notomi, “Large tunable fractional delay of slow light pulse and its application to fast optical correlator,” Opt. Express |

11. | L. Gu, W. Jiang, X. Chen, L. Wang, and R. T. Chen, “High speed silicon photonic crystal waveguide modulator for low voltage operation,” Appl. Phys. Lett. |

12. | M. Chahal, G. K. Celler, Y. Jaluria, and W. Jiang, “Thermo-optic characteristics and switching power limit of slow-light photonic crystal structures on a silicon-on-insulator platform,” Opt. Express |

13. | Y. Jaluria, |

14. | Y. Jaluria, |

15. | R. F. David, “Computerized thermal analysis of hybrid circuits,” IEEE Trans. Parts Hybrids Packag. |

16. | F. N. Masana, “A closed form solution of junction to substrate thermal resistance in semiconductor chips,” IEEE Trans. Comp. Packag, Manufact. Technol. |

17. | W. H. Hayt and J. A. Buck, |

18. | F. P. Incropera, D. P. Dewitt, T. L. Bergman, and A. S. Lavine, |

19. | W. Song, R. A. Integlia, and W. Jiang, “Slow light loss due to roughness in photonic crystal waveguides: an analytic approach,” Phys. Rev. B |

20. | M. Y. Chen, H. Subbaraman, and R. T. Chen, “Photonic crystal fiber beamformer for multiple X band phased-array antenna transmissions,” IEEE Photon. Technol. Lett. |

21. | E. Brookner, |

22. | J. A. Rogers, M. G. Lagally, and R. G. Nuzzo, “Synthesis assembly and applications of semiconductor nanomembranes,” Nature |

23. | S. Huang, J. Luo, H. L. Yip, A. Ayazi, X. H. Zhou, M. Gould, A. Chen, T. Baehr-Jones, M. Hochberg, and A. K. Y. Jen, “Efficient poling of electro-optic polymers in thin films and silicon slot waveguides by detachable pyroelectric crystals,” Adv. Mater. (Deerfield Beach Fla.) |

**OCIS Codes**

(120.6810) Instrumentation, measurement, and metrology : Thermal effects

(350.4238) Other areas of optics : Nanophotonics and photonic crystals

(130.4815) Integrated optics : Optical switching devices

(130.5296) Integrated optics : Photonic crystal waveguides

**ToC Category:**

Photonic Crystals

**History**

Original Manuscript: November 9, 2012

Revised Manuscript: December 17, 2012

Manuscript Accepted: December 19, 2012

Published: February 12, 2013

**Citation**

Weiwei Song, Manjit Chahal, George K. Celler, Yogesh Jaluria, Graham T. Reed, and Wei Jiang, "The influence of substrate on SOI photonic crystal thermo-optic devices," Opt. Express **21**, 4235-4243 (2013)

http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-21-4-4235

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### References

- R. A. Soref, “The past, present, and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron.12(6), 1678–1687 (2006). [CrossRef]
- G. T. Reed, ed., Silicon Photonics: the State of the Art (Wiley, 2008).
- G. K. Celler and S. Cristoloveanu, “Frontiers of silicon-on-insulator,” J. Appl. Phys.93(9), 4955–4978 (2003). [CrossRef]
- L. Gu, W. Jiang, X. Chen, and R. T. Chen, “Physical mechanism of p-i-n diode based photonic crystal silicon electrooptic modulators for gigahertz operation,” IEEE J. Sel. Top. Quantum Electron.14(4), 1132–1139 (2008). [CrossRef]
- Y. A. Vlasov, M. O’Boyle, H. F. Hamann, and S. J. McNab, “Active control of slow light on a chip with photonic crystal waveguides,” Nature438(7064), 65–69 (2005). [CrossRef] [PubMed]
- M. T. Tinker and J.-B. Lee, “Thermal and optical simulation of a photonic crystal light modulator based on the thermo-optic shift of the cut-off frequency,” Opt. Express13(18), 7174–7188 (2005). [CrossRef] [PubMed]
- T. Chu, H. Yamada, S. Ishida, and Y. Arakawa, “Thermooptic switch based on photonic-crystal line-defect waveguides,” IEEE Photon. Technol. Lett.17(10), 2083–2085 (2005). [CrossRef]
- L. Gu, W. Jiang, X. Chen, and R. T. Chen, “Thermooptically tuned photonic crystal waveguide silicon-on-insulator Mach-Zehnder interferometers,” IEEE Photon. Technol. Lett.19(5), 342–344 (2007). [CrossRef]
- D. M. Beggs, T. P. White, L. O’Faolain, and T. F. Krauss, “Ultracompact and low-power optical switch based on silicon photonic crystals,” Opt. Lett.33(2), 147–149 (2008). [CrossRef] [PubMed]
- N. Ishikura, T. Baba, E. Kuramochi, and M. Notomi, “Large tunable fractional delay of slow light pulse and its application to fast optical correlator,” Opt. Express19(24), 24102–24108 (2011). [CrossRef] [PubMed]
- L. Gu, W. Jiang, X. Chen, L. Wang, and R. T. Chen, “High speed silicon photonic crystal waveguide modulator for low voltage operation,” Appl. Phys. Lett.90(7), 071105 (2007). [CrossRef]
- M. Chahal, G. K. Celler, Y. Jaluria, and W. Jiang, “Thermo-optic characteristics and switching power limit of slow-light photonic crystal structures on a silicon-on-insulator platform,” Opt. Express20(4), 4225–4231 (2012). [CrossRef] [PubMed]
- Y. Jaluria, Design and Optimization of Thermal Systems, 2nd ed. (CRC Press, 2008).
- Y. Jaluria, Natural Convection Heat and Mass Transfer. (Pergamon Press, 1980).
- R. F. David, “Computerized thermal analysis of hybrid circuits,” IEEE Trans. Parts Hybrids Packag.13(3), 283–290 (1977). [CrossRef]
- F. N. Masana, “A closed form solution of junction to substrate thermal resistance in semiconductor chips,” IEEE Trans. Comp. Packag, Manufact. Technol.19, 539–545 (1996).
- W. H. Hayt and J. A. Buck, Engineering Electromagnetics, 7th ed. (McGraw-Hill, 2006).
- F. P. Incropera, D. P. Dewitt, T. L. Bergman, and A. S. Lavine, Fundamentals of Heat and Mass Transfer, 6th ed. (Wiley, 2007).
- W. Song, R. A. Integlia, and W. Jiang, “Slow light loss due to roughness in photonic crystal waveguides: an analytic approach,” Phys. Rev. B82(23), 235306 (2010). [CrossRef]
- M. Y. Chen, H. Subbaraman, and R. T. Chen, “Photonic crystal fiber beamformer for multiple X band phased-array antenna transmissions,” IEEE Photon. Technol. Lett.20(5), 375–377 (2008). [CrossRef]
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