## Optical interferometric logic gates based on metal slot waveguide network realizing whole fundamental logic operations |

Optics Express, Vol. 21, Issue 8, pp. 9556-9562 (2013)

http://dx.doi.org/10.1364/OE.21.009556

Acrobat PDF (1986 KB)

### Abstract

Optical interferometric logic gates in metal slot waveguide network are designed and investigated by electromagnetic simulations. The designed logic gates can realize all fundamental logic operations. A single Y-shaped junction can work as logic gate for four logic functions: AND, NOT, OR and XOR. By cascading two Y-shaped junctions, NAND, NOR and XNOR can be realized. The working principle is analyzed in detail. In the simulations, these gates show large intensity contrast for the Boolean logic states of the output. These results can be useful for future integrated optical computing.

© 2013 OSA

## 1. Introduction

1. H. J. Caulfield and S. Dolev, “Why future supercomputing requires optics,” Nat. Photonics **4**(5), 261–263 (2010). [CrossRef]

2. H. J. Caulfield and J. Westphal, “The logic of optics and the optics of logic,” Inf. Sci. **162**(1), 21–33 (2004). [CrossRef]

4. Y. Zhang, Y. Zhang, and B. Li, “Optical switches and logic gates based on self-collimated beams in two-dimensional photonic crystals,” Opt. Express **15**(15), 9287–9292 (2007). [CrossRef] [PubMed]

5. V. R. Almeida, C. A. Barrios, R. R. Panepucci, and M. Lipson, “All-optical control of light on a silicon chip,” Nature **431**(7012), 1081–1084 (2004). [CrossRef] [PubMed]

6. Q. Xu and M. Lipson, “All-optical logic based on silicon micro-ring resonators,” Opt. Express **15**(3), 924–929 (2007). [CrossRef] [PubMed]

7. T. Holmgaard and S. I. Bozhevolnyi, “Theoretical analysis of dielectric-loaded surface plasmon-polariton waveguides,” Phys. Rev. B **75**(24), 245405 (2007). [CrossRef]

10. R. M. Dickson and L. A. Lyon, “Unidirectional Plasmon Propagation in Metallic Nanowires,” J. Phys. Chem. B **104**(26), 6095–6098 (2000). [CrossRef]

11. A. V. Krasavin and A. V. Zayats, “Passive photonic elements based on dielectric-loaded surface plasmon polariton waveguides,” Appl. Phys. Lett. **90**(21), 211101 (2007). [CrossRef]

16. H. Wei, Z. Wang, X. Tian, M. Käll, and H. Xu, “Cascaded logic gates in nanophotonic plasmon networks,” Nat Commun **2**, 387 (2011). [CrossRef] [PubMed]

15. H. Wei, Z. Li, X. Tian, Z. Wang, F. Cong, N. Liu, S. Zhang, P. Nordlander, N. J. Halas, and H. Xu, “Quantum Dot-Based Local Field Imaging Reveals Plasmon-Based Interferometric Logic in Silver Nanowire Networks,” Nano Lett. **11**(2), 471–475 (2011). [CrossRef] [PubMed]

16. H. Wei, Z. Wang, X. Tian, M. Käll, and H. Xu, “Cascaded logic gates in nanophotonic plasmon networks,” Nat Commun **2**, 387 (2011). [CrossRef] [PubMed]

17. Y. Fu, X. Hu, C. Lu, S. Yue, H. Yang, and Q. Gong, “All-Optical Logic Gates Based on Nanoscale Plasmonic Slot Waveguides,” Nano Lett. **12**(11), 5784–5790 (2012). [CrossRef] [PubMed]

## 2. Logic gates with two input ports

_{2}substrate. In the device, the two ports denoted by I

_{1}and I

_{2}are taken as channels for input signals. The remainder port denoted by O is used as the fan-out of the logic gate. The input and output are all encoded by their intensities. Two signals are transmitted to the junction from the input ports and then reach the output port. The amplitudes of transmitted powers for the two signals are E(I

_{1}) and E(I

_{2}). The constructive or destructive interference of E(I

_{1}) and E(I

_{2}), which is determined by the phases of the input signals, result in the output intensity I

_{o}. By defining the value of the threshold intensity, the three port device can realize the logic operations of AND, OR, NOT and XOR gates.

_{1}),E(I

_{2})}, using the amplitudes of transmitted powers. The input power at ports I

_{1}and I

_{2}is selected to be equal. For the inputs, “on” and “off” states correspond to “1” and “0”, respectively. For the output, the Boolean value is determined by the threshold intensity I

_{t}. If the output intensity I

_{o}is larger than the threshold I

_{t}, the output value is “1”. If I

_{o}<I

_{t}, the output is “0”. For constructive interference, the complex amplitudes of the output for individual input E(I

_{1}) and E(I

_{2}) are set to be E. The output intensity I

_{o}is |E|

^{2}for inputs {E,0} and {0,E}, and 4|E|

^{2}for input {E,E}. When choosing I

_{t}below |E|

^{2}, the output state is “1” for input {E,0}, {0,E} and {E,E}, realizing OR logic function. When I

_{t}is chosen above |E|

^{2}and below 4|E|

^{2}, the output is “1” only for {E,E} input, corresponding to the AND logic operations. For destructive interference, the complex amplitudes of the output for individual input E(I

_{1}) and E(I

_{2}) are E or –E, respectively. Because of the symmetry of gate structure, complete destructive interference can be realized at port O, resulting in a large interference visibility. The output intensity I

_{o}is |E|

^{2}for inputs {E,0} and {0,-E}, and 0 for {E, -E}. Choosing I

_{t}below |E|

^{2}results in an XOR gate. If the signal at port I

_{2}is used as control signal, for the input 0 and E at the I

_{1}port, i.e. {0,-E} and {E, -E}, the output state is just opposite to the input state, which leads to the function of NOT gate.

18. P. B. Johnson and R. W. Christy, “Optical constants of the noble metals,” Phys. Rev. B **6**(12), 4370–4379 (1972). [CrossRef]

_{2}used here is 2.13. To obtain good confinement and acceptable loss, the thickness t and width of waveguide d is set to be: t = 100nm and d = 60nm. The corresponding fundamental mode distribution is shown in Fig. 2(a). As can be seen the electric field is mainly confined in the slot. At the wavelength, the slot waveguide also have a considerable propagation length of 5.33μm. Here, the propagation length is defined as the length over which the power in the direction of propagation decays to 1/e of its original value due to material losses. In the gate structure, the input light propagating to the output port O will suffer strong loss at the junction. To decrease the energy loss at the junction, small angle between the two input waveguide θ is preferred. But too small θ will decrease the separation between the two input waveguide w, leading to the cross talk. To determine the appropriate value of the separation w, coupling length of two parallel slot waveguides for different separations is calculated, as shown in Fig. 2(b). Here the coupling length is defined as the propagating distance over which the power coupled from one waveguide to the other reaches the maximum. After overall consideration, θ is chosen to be 30°, and w is 300 nm. In the simulations, all the bends in the structures are used as sharp corners. In practical experiment, these corners have round shapes, which is beneficial for decreasing the bending loss.

_{1}and I

_{2}is I

_{0}, but the initial phase differences Δφ of the two signals is adjustable. The Fig. 3(a) shows the output power, I

_{o}(I

_{1},I

_{2}), for different Δφ. I

_{o}(I

_{1},I

_{2}) shows an ideal interference of the two input light signals, which is well described by cosine function. The complete interference can be attributed to the single mode characteristic of the waveguide and the symmetry of the gate structure. The output powers for individual input I

_{o}(I

_{1}) and I

_{o}(I

_{2}) are shown as the blue line. Our designed logic functions can be realized at different values of Δφ by defining corresponding threshold intensity. For Δφ = π and threshold value of 0.2I

_{0}, XOR or NOT operations can be realized. For Δφ = 2π and threshold value of 0.2I

_{0}, the device functions as an OR gate. If the threshold is increased to I

_{0}, the AND logic gate is realized. Figures 3(b)-3(d) show the field intensity distribution in the device for single input and both inputs with different Δφ. It is noteworthy that the intensity contrast for the output value “1” and “0” is high, for example, the intensity contrast is about 16dB for XOR, NOT and OR operations, and about 6dB for AND operations. It should also be noted that the choice of the threshold intensity and the phase difference can be quite flexible. For a given threshold intensity, these logic operations can be realized in a wide range of Δφ, which makes the devices have large tolerance.

## 3. Logic gates with three input ports

16. H. Wei, Z. Wang, X. Tian, M. Käll, and H. Xu, “Cascaded logic gates in nanophotonic plasmon networks,” Nat Commun **2**, 387 (2011). [CrossRef] [PubMed]

_{1}and I

_{2}, are connected to a Y-shape junction G

_{1}, which can independently operate as a logic gate. The output of G

_{1}and another input port C are connected, forming a second independent gate, named G

_{2}. The output port of G

_{2}is denoted as port O. In this design, the output of the first operation in G

_{1}is used as the input signal of G

_{2}. Thus cascaded logic gates can be realized in such structure. The ports I

_{1}and I

_{2}are used for input signals, while the port C is used for control signal. Port O is the fan-out of the whole structure. All the parameters are denoted similar as in last section. The complex amplitude of light in port O transmitted from port C is denoted as E(C). For further extension of the device to realize more complex functions, the geometries of the basic gates, for instance G

_{1}and G

_{2}, are exactly the same.

_{1}and I

_{2}are in phase (Fig. 3(a) and Table 1). An out-phase control signal from port C can inverse the output of G

_{1}. Here the second gate G

_{2}operates as a NOT gate. As shown in Table 2, when E(C) is twice as E(I

_{1}) and E(I

_{2}) (E(I

_{1}) = E(I

_{2}) = E), with a phase difference of π, NOR and NAND operations can be obtained. For a threshold value I

_{t}above |E|

^{2}and below 4|E|

^{2}, the output correspond to NOR logic operation. For a threshold value I

_{t}below |E|

^{2}, the logic function of the whole structure is NAND. The cascade approach for constructing NOR and NAND is not applicable for XNOR. For XOR operation, the output for input patterns {E,0} and {0,-E} are out phase. An additional control signal will lead to different output result for the two input patterns. However, the XNOR operation can still be realized in the structure with three input ports. Table 2 shows that, when E(I

_{1}) = E(I

_{2}) = E and the control signal is out-phase with E(C) = -E, the outputs correspond to XNOR operation for a threshold value below |E|

^{2}.

_{1}and I

_{2}, their equal distance to port O produces no additional phase difference. So the two input signals are set to be with equal phase at the two ports. By setting the input power at port I

_{1}, I

_{2}and C equal to I

_{0}, the output intensity at port O is calculated for varying phase difference between the control signal and the input signals, as shown in Fig. 5(a). The minimum of the output power, corresponding to destructive interference at port O, occurs at Δφ = 1.1π, which is determined by the difference of the distances travelled by the control signal and the input signals. This phase difference is fixed for latter simulations. Figure 5(b) shows the variation of the output power at port O for different inputs when the power of control signal I

_{C}is increased. The red crosses mark the corresponding area and power threshold for the three logic functions. As an example of the three logic functions, the distribution of field intensity for operating XNOR gate is shown in Fig. 6, with the power of control beam I

_{C}to be 0.58I

_{0}. This XNOR logic gate shows a high intensity contrast of the output states “1” and “0” as about 16dB.

## 4. Conclusion

## Acknowledgments

## References and links

1. | H. J. Caulfield and S. Dolev, “Why future supercomputing requires optics,” Nat. Photonics |

2. | H. J. Caulfield and J. Westphal, “The logic of optics and the optics of logic,” Inf. Sci. |

3. | L. Qian and H. J. Caulfield, “What can we do with a linear optical logic gate?” Inf. Sci. |

4. | Y. Zhang, Y. Zhang, and B. Li, “Optical switches and logic gates based on self-collimated beams in two-dimensional photonic crystals,” Opt. Express |

5. | V. R. Almeida, C. A. Barrios, R. R. Panepucci, and M. Lipson, “All-optical control of light on a silicon chip,” Nature |

6. | Q. Xu and M. Lipson, “All-optical logic based on silicon micro-ring resonators,” Opt. Express |

7. | T. Holmgaard and S. I. Bozhevolnyi, “Theoretical analysis of dielectric-loaded surface plasmon-polariton waveguides,” Phys. Rev. B |

8. | G. Veronis and S. Fan, “Guided subwavelength plasmonic mode supported by a slot in a thin metal film,” Opt. Lett. |

9. | S. I. Bozhevolnyi, V. S. Volkov, E. Devaux, and T. W. Ebbesen, “Channel plasmon-polariton guiding by subwavelength metal grooves,” Phys. Rev. Lett. |

10. | R. M. Dickson and L. A. Lyon, “Unidirectional Plasmon Propagation in Metallic Nanowires,” J. Phys. Chem. B |

11. | A. V. Krasavin and A. V. Zayats, “Passive photonic elements based on dielectric-loaded surface plasmon polariton waveguides,” Appl. Phys. Lett. |

12. | S. I. Bozhevolnyi, V. S. Volkov, E. Devaux, J. Y. Laluet, and T. W. Ebbesen, “Channel plasmon subwavelength waveguide components including interferometers and ring resonators,” Nature |

13. | G. Veronis and S. Fan, “Bends and splitters in metal-dielectirc-metal subwavelength plasmonic waveguides,” Appl. Phys. Lett. |

14. | Y. Fang, Z. Li, Y. Huang, S. Zhang, P. Nordlander, N. J. Halas, and H. Xu, “Branched Silver Nanowires as Controllable Plasmon Routers,” Nano Lett. |

15. | H. Wei, Z. Li, X. Tian, Z. Wang, F. Cong, N. Liu, S. Zhang, P. Nordlander, N. J. Halas, and H. Xu, “Quantum Dot-Based Local Field Imaging Reveals Plasmon-Based Interferometric Logic in Silver Nanowire Networks,” Nano Lett. |

16. | H. Wei, Z. Wang, X. Tian, M. Käll, and H. Xu, “Cascaded logic gates in nanophotonic plasmon networks,” Nat Commun |

17. | Y. Fu, X. Hu, C. Lu, S. Yue, H. Yang, and Q. Gong, “All-Optical Logic Gates Based on Nanoscale Plasmonic Slot Waveguides,” Nano Lett. |

18. | P. B. Johnson and R. W. Christy, “Optical constants of the noble metals,” Phys. Rev. B |

**OCIS Codes**

(200.4660) Optics in computing : Optical logic

(230.7370) Optical devices : Waveguides

(250.5403) Optoelectronics : Plasmonics

**ToC Category:**

Optics in Computing

**History**

Original Manuscript: January 24, 2013

Revised Manuscript: March 13, 2013

Manuscript Accepted: March 13, 2013

Published: April 10, 2013

**Citation**

Deng Pan, Hong Wei, and Hongxing Xu, "Optical interferometric logic gates based on metal slot waveguide network realizing whole fundamental logic operations," Opt. Express **21**, 9556-9562 (2013)

http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-21-8-9556

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### References

- H. J. Caulfield and S. Dolev, “Why future supercomputing requires optics,” Nat. Photonics4(5), 261–263 (2010). [CrossRef]
- H. J. Caulfield and J. Westphal, “The logic of optics and the optics of logic,” Inf. Sci.162(1), 21–33 (2004). [CrossRef]
- L. Qian and H. J. Caulfield, “What can we do with a linear optical logic gate?” Inf. Sci.176(22), 3379–3392 (2006). [CrossRef]
- Y. Zhang, Y. Zhang, and B. Li, “Optical switches and logic gates based on self-collimated beams in two-dimensional photonic crystals,” Opt. Express15(15), 9287–9292 (2007). [CrossRef] [PubMed]
- V. R. Almeida, C. A. Barrios, R. R. Panepucci, and M. Lipson, “All-optical control of light on a silicon chip,” Nature431(7012), 1081–1084 (2004). [CrossRef] [PubMed]
- Q. Xu and M. Lipson, “All-optical logic based on silicon micro-ring resonators,” Opt. Express15(3), 924–929 (2007). [CrossRef] [PubMed]
- T. Holmgaard and S. I. Bozhevolnyi, “Theoretical analysis of dielectric-loaded surface plasmon-polariton waveguides,” Phys. Rev. B75(24), 245405 (2007). [CrossRef]
- G. Veronis and S. Fan, “Guided subwavelength plasmonic mode supported by a slot in a thin metal film,” Opt. Lett.30(24), 3359–3361 (2005). [CrossRef] [PubMed]
- S. I. Bozhevolnyi, V. S. Volkov, E. Devaux, and T. W. Ebbesen, “Channel plasmon-polariton guiding by subwavelength metal grooves,” Phys. Rev. Lett.95(4), 046802 (2005). [CrossRef] [PubMed]
- R. M. Dickson and L. A. Lyon, “Unidirectional Plasmon Propagation in Metallic Nanowires,” J. Phys. Chem. B104(26), 6095–6098 (2000). [CrossRef]
- A. V. Krasavin and A. V. Zayats, “Passive photonic elements based on dielectric-loaded surface plasmon polariton waveguides,” Appl. Phys. Lett.90(21), 211101 (2007). [CrossRef]
- S. I. Bozhevolnyi, V. S. Volkov, E. Devaux, J. Y. Laluet, and T. W. Ebbesen, “Channel plasmon subwavelength waveguide components including interferometers and ring resonators,” Nature440(7083), 508–511 (2006). [CrossRef] [PubMed]
- G. Veronis and S. Fan, “Bends and splitters in metal-dielectirc-metal subwavelength plasmonic waveguides,” Appl. Phys. Lett.87(13), 131102 (2005). [CrossRef]
- Y. Fang, Z. Li, Y. Huang, S. Zhang, P. Nordlander, N. J. Halas, and H. Xu, “Branched Silver Nanowires as Controllable Plasmon Routers,” Nano Lett.10(5), 1950–1954 (2010). [CrossRef] [PubMed]
- H. Wei, Z. Li, X. Tian, Z. Wang, F. Cong, N. Liu, S. Zhang, P. Nordlander, N. J. Halas, and H. Xu, “Quantum Dot-Based Local Field Imaging Reveals Plasmon-Based Interferometric Logic in Silver Nanowire Networks,” Nano Lett.11(2), 471–475 (2011). [CrossRef] [PubMed]
- H. Wei, Z. Wang, X. Tian, M. Käll, and H. Xu, “Cascaded logic gates in nanophotonic plasmon networks,” Nat Commun2, 387 (2011). [CrossRef] [PubMed]
- Y. Fu, X. Hu, C. Lu, S. Yue, H. Yang, and Q. Gong, “All-Optical Logic Gates Based on Nanoscale Plasmonic Slot Waveguides,” Nano Lett.12(11), 5784–5790 (2012). [CrossRef] [PubMed]
- P. B. Johnson and R. W. Christy, “Optical constants of the noble metals,” Phys. Rev. B6(12), 4370–4379 (1972). [CrossRef]

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