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Optics Express

  • Editor: Andrew M. Weiner
  • Vol. 21, Iss. 8 — Apr. 22, 2013
  • pp: 9556–9562
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Optical interferometric logic gates based on metal slot waveguide network realizing whole fundamental logic operations

Deng Pan, Hong Wei, and Hongxing Xu  »View Author Affiliations


Optics Express, Vol. 21, Issue 8, pp. 9556-9562 (2013)
http://dx.doi.org/10.1364/OE.21.009556


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Abstract

Optical interferometric logic gates in metal slot waveguide network are designed and investigated by electromagnetic simulations. The designed logic gates can realize all fundamental logic operations. A single Y-shaped junction can work as logic gate for four logic functions: AND, NOT, OR and XOR. By cascading two Y-shaped junctions, NAND, NOR and XNOR can be realized. The working principle is analyzed in detail. In the simulations, these gates show large intensity contrast for the Boolean logic states of the output. These results can be useful for future integrated optical computing.

© 2013 OSA

1. Introduction

As is known, semiconductor-based electronic devices will reach their limit in near future. Photonic devices and circuits have been proposed to break this limitation, benefiting from the fast speed and low heat producing properties of photons [1

1. H. J. Caulfield and S. Dolev, “Why future supercomputing requires optics,” Nat. Photonics 4(5), 261–263 (2010). [CrossRef]

]. The elementary units of electronic circuits are transistor based Boolean logic gates. In photonics circuits, logic functions can be realized by linear interferences [2

2. H. J. Caulfield and J. Westphal, “The logic of optics and the optics of logic,” Inf. Sci. 162(1), 21–33 (2004). [CrossRef]

4

4. Y. Zhang, Y. Zhang, and B. Li, “Optical switches and logic gates based on self-collimated beams in two-dimensional photonic crystals,” Opt. Express 15(15), 9287–9292 (2007). [CrossRef] [PubMed]

] or by nonlinear optical processes [5

5. V. R. Almeida, C. A. Barrios, R. R. Panepucci, and M. Lipson, “All-optical control of light on a silicon chip,” Nature 431(7012), 1081–1084 (2004). [CrossRef] [PubMed]

,6

6. Q. Xu and M. Lipson, “All-optical logic based on silicon micro-ring resonators,” Opt. Express 15(3), 924–929 (2007). [CrossRef] [PubMed]

]. For linear optical logic gates, the constructive or destructive interference of the input signals yields corresponding logic operation results, which show merits of good stability and extensibility.

The integration of the photonic devices is limited by diffraction of light. Surface plasmon polaritons (SPPs), which are localized surface electromagnetic waves at the interface of metal and dielectric, can be applied to overcome this limitation. Many kinds of plasmonic waveguides [7

7. T. Holmgaard and S. I. Bozhevolnyi, “Theoretical analysis of dielectric-loaded surface plasmon-polariton waveguides,” Phys. Rev. B 75(24), 245405 (2007). [CrossRef]

10

10. R. M. Dickson and L. A. Lyon, “Unidirectional Plasmon Propagation in Metallic Nanowires,” J. Phys. Chem. B 104(26), 6095–6098 (2000). [CrossRef]

] and devices [11

11. A. V. Krasavin and A. V. Zayats, “Passive photonic elements based on dielectric-loaded surface plasmon polariton waveguides,” Appl. Phys. Lett. 90(21), 211101 (2007). [CrossRef]

16

16. H. Wei, Z. Wang, X. Tian, M. Käll, and H. Xu, “Cascaded logic gates in nanophotonic plasmon networks,” Nat Commun 2, 387 (2011). [CrossRef] [PubMed]

] have been proposed. We recently in experiment realized optical Boolean logic gates based on propagating plasmons on silver nanowires, and showed the integration potential by realizing NOR gate through cascading OR and NOT gates [15

15. H. Wei, Z. Li, X. Tian, Z. Wang, F. Cong, N. Liu, S. Zhang, P. Nordlander, N. J. Halas, and H. Xu, “Quantum Dot-Based Local Field Imaging Reveals Plasmon-Based Interferometric Logic in Silver Nanowire Networks,” Nano Lett. 11(2), 471–475 (2011). [CrossRef] [PubMed]

,16

16. H. Wei, Z. Wang, X. Tian, M. Käll, and H. Xu, “Cascaded logic gates in nanophotonic plasmon networks,” Nat Commun 2, 387 (2011). [CrossRef] [PubMed]

]. Compared with silver nanowires, the metal slot waveguides show good field confinement, and can be easily integrated to complex structures and networks. Therefore, slot-waveguide-based plasmonic devices have large potential to be employed for on-chip integration. Recently, optical logic gates in metal slot waveguides have been proposed [17

17. Y. Fu, X. Hu, C. Lu, S. Yue, H. Yang, and Q. Gong, “All-Optical Logic Gates Based on Nanoscale Plasmonic Slot Waveguides,” Nano Lett. 12(11), 5784–5790 (2012). [CrossRef] [PubMed]

]. However, the working principle of this kind logic gates has not yet been discussed in detail.

In this paper, we realize the whole set of fundamental logic gates using two kinds of structures formed by metal slot waveguides. A single Y-shaped waveguide structure can work as AND, OR, NOT and XOR logic gates. By using two cascaded Y-shaped structure, with one port for inputting control beam, NAND, NOR and XNOR can be realized. The working principle is discussed in detail and the working efficiency is verified by simulation. The metal slot waveguide based logic gates show small size and intensity contrast as high as 16dB. These gates are good candidates for constructing future optical computing chips.

2. Logic gates with two input ports

The proposed logic gates are composed by three metal slot waveguides with a Y-shape junction as shown in Fig. 1
Fig. 1 Sketch of two input port logic gate based on slots in Ag film.
. The structure is fabricated in sliver film coated on SiO2 substrate. In the device, the two ports denoted by I1 and I2 are taken as channels for input signals. The remainder port denoted by O is used as the fan-out of the logic gate. The input and output are all encoded by their intensities. Two signals are transmitted to the junction from the input ports and then reach the output port. The amplitudes of transmitted powers for the two signals are E(I1) and E(I2). The constructive or destructive interference of E(I1) and E(I2), which is determined by the phases of the input signals, result in the output intensity Io. By defining the value of the threshold intensity, the three port device can realize the logic operations of AND, OR, NOT and XOR gates.

The working principle for the logic operations is illustrated in Table 1

Table 1. Illustration of the working principle of two input ports gates

table-icon
View This Table
| View All Tables
. The input is expressed as {E(I1),E(I2)}, using the amplitudes of transmitted powers. The input power at ports I1 and I2 is selected to be equal. For the inputs, “on” and “off” states correspond to “1” and “0”, respectively. For the output, the Boolean value is determined by the threshold intensity It. If the output intensity Io is larger than the threshold It, the output value is “1”. If Io<It, the output is “0”. For constructive interference, the complex amplitudes of the output for individual input E(I1) and E(I2) are set to be E. The output intensity Io is |E|2 for inputs {E,0} and {0,E}, and 4|E|2 for input {E,E}. When choosing It below |E|2, the output state is “1” for input {E,0}, {0,E} and {E,E}, realizing OR logic function. When It is chosen above |E|2 and below 4|E|2, the output is “1” only for {E,E} input, corresponding to the AND logic operations. For destructive interference, the complex amplitudes of the output for individual input E(I1) and E(I2) are E or –E, respectively. Because of the symmetry of gate structure, complete destructive interference can be realized at port O, resulting in a large interference visibility. The output intensity Io is |E|2 for inputs {E,0} and {0,-E}, and 0 for {E, -E}. Choosing It below |E|2 results in an XOR gate. If the signal at port I2 is used as control signal, for the input 0 and E at the I1 port, i.e. {0,-E} and {E, -E}, the output state is just opposite to the input state, which leads to the function of NOT gate.

To verify the functions of the logic gate, simulations based on finite element method are performed. In simulation, we pay attention to the wavelength of 632.8 nm, with the corresponding permittivity of silver −18.36 + 0.48i, interpolated from experimental data [18

18. P. B. Johnson and R. W. Christy, “Optical constants of the noble metals,” Phys. Rev. B 6(12), 4370–4379 (1972). [CrossRef]

]. The permittivity value of SiO2 used here is 2.13. To obtain good confinement and acceptable loss, the thickness t and width of waveguide d is set to be: t = 100nm and d = 60nm. The corresponding fundamental mode distribution is shown in Fig. 2(a)
Fig. 2 (a) Distribution of field intensity |E| 2 of fundamental mode in the simulated metal slot waveguide. (b) Coupling length of two parallel slot waveguide as a function of separation w.
. As can be seen the electric field is mainly confined in the slot. At the wavelength, the slot waveguide also have a considerable propagation length of 5.33μm. Here, the propagation length is defined as the length over which the power in the direction of propagation decays to 1/e of its original value due to material losses. In the gate structure, the input light propagating to the output port O will suffer strong loss at the junction. To decrease the energy loss at the junction, small angle between the two input waveguide θ is preferred. But too small θ will decrease the separation between the two input waveguide w, leading to the cross talk. To determine the appropriate value of the separation w, coupling length of two parallel slot waveguides for different separations is calculated, as shown in Fig. 2(b). Here the coupling length is defined as the propagating distance over which the power coupled from one waveguide to the other reaches the maximum. After overall consideration, θ is chosen to be 30°, and w is 300 nm. In the simulations, all the bends in the structures are used as sharp corners. In practical experiment, these corners have round shapes, which is beneficial for decreasing the bending loss.

In the simulation, the power of signals on both input port I1 and I2 is I0, but the initial phase differences Δφ of the two signals is adjustable. The Fig. 3(a)
Fig. 3 Simulation results for the working performance of two input port logic gate. (a) The output power at port O as a function of phase difference between two input signals. The power of two input signals is both I0. (b-d) Distribution of field intensity |E|2 for individual inputs. (b) only one input at port 2; (c) two input signals with Δφ = 2π; (d) two input signals with Δφ = π.
shows the output power, Io(I1,I2), for different Δφ. Io(I1,I2) shows an ideal interference of the two input light signals, which is well described by cosine function. The complete interference can be attributed to the single mode characteristic of the waveguide and the symmetry of the gate structure. The output powers for individual input Io(I1) and Io(I2) are shown as the blue line. Our designed logic functions can be realized at different values of Δφ by defining corresponding threshold intensity. For Δφ = π and threshold value of 0.2I0, XOR or NOT operations can be realized. For Δφ = 2π and threshold value of 0.2I0, the device functions as an OR gate. If the threshold is increased to I0, the AND logic gate is realized. Figures 3(b)-3(d) show the field intensity distribution in the device for single input and both inputs with different Δφ. It is noteworthy that the intensity contrast for the output value “1” and “0” is high, for example, the intensity contrast is about 16dB for XOR, NOT and OR operations, and about 6dB for AND operations. It should also be noted that the choice of the threshold intensity and the phase difference can be quite flexible. For a given threshold intensity, these logic operations can be realized in a wide range of Δφ, which makes the devices have large tolerance.

3. Logic gates with three input ports

For logic gates NOR, NAND and NXOR, the output is “1” when both input ports are empty, so additional input of the logic gate is needed to work as control signal. From another point of view, these logic functions are composite operations of the former functions, and their gates can be realized by cascading NOT gate and OR, AND, XOR, respectively [16

16. H. Wei, Z. Wang, X. Tian, M. Käll, and H. Xu, “Cascaded logic gates in nanophotonic plasmon networks,” Nat Commun 2, 387 (2011). [CrossRef] [PubMed]

]. The sketched structure of the logic gate with three input ports is shown in Fig. 4
Fig. 4 Sketch of three input ports logic gate
. In the structure, two input ports, I1 and I2, are connected to a Y-shape junction G1, which can independently operate as a logic gate. The output of G1 and another input port C are connected, forming a second independent gate, named G2. The output port of G2 is denoted as port O. In this design, the output of the first operation in G1 is used as the input signal of G2. Thus cascaded logic gates can be realized in such structure. The ports I1 and I2 are used for input signals, while the port C is used for control signal. Port O is the fan-out of the whole structure. All the parameters are denoted similar as in last section. The complex amplitude of light in port O transmitted from port C is denoted as E(C). For further extension of the device to realize more complex functions, the geometries of the basic gates, for instance G1 and G2, are exactly the same.

The working principle of the gate is analyzed as shown in Table 2

Table 2. Illustration of the working principle of the three input ports gates

table-icon
View This Table
| View All Tables
. For operations OR and AND, the two input signals from port I1 and I2 are in phase (Fig. 3(a) and Table 1). An out-phase control signal from port C can inverse the output of G1. Here the second gate G2 operates as a NOT gate. As shown in Table 2, when E(C) is twice as E(I1) and E(I2) (E(I1) = E(I2) = E), with a phase difference of π, NOR and NAND operations can be obtained. For a threshold value It above |E|2 and below 4|E|2, the output correspond to NOR logic operation. For a threshold value It below |E|2, the logic function of the whole structure is NAND. The cascade approach for constructing NOR and NAND is not applicable for XNOR. For XOR operation, the output for input patterns {E,0} and {0,-E} are out phase. An additional control signal will lead to different output result for the two input patterns. However, the XNOR operation can still be realized in the structure with three input ports. Table 2 shows that, when E(I1) = E(I2) = E and the control signal is out-phase with E(C) = -E, the outputs correspond to XNOR operation for a threshold value below |E|2.

Electromagnetic calculations were performed to quantitatively investigate the outputs of the device. For ports I1 and I2, their equal distance to port O produces no additional phase difference. So the two input signals are set to be with equal phase at the two ports. By setting the input power at port I1, I2 and C equal to I0, the output intensity at port O is calculated for varying phase difference between the control signal and the input signals, as shown in Fig. 5(a)
Fig. 5 (a) Output power for various phase difference between control beam and signals. (b) Output power for different input power of control beam. In (b), the red crosses correspond to working states for different operations.
. The minimum of the output power, corresponding to destructive interference at port O, occurs at Δφ = 1.1π, which is determined by the difference of the distances travelled by the control signal and the input signals. This phase difference is fixed for latter simulations. Figure 5(b) shows the variation of the output power at port O for different inputs when the power of control signal IC is increased. The red crosses mark the corresponding area and power threshold for the three logic functions. As an example of the three logic functions, the distribution of field intensity for operating XNOR gate is shown in Fig. 6
Fig. 6 Distribution of field intensity |E|2 for XNOR logic operations. (a), (b), (c) and (d) correspond to different input patterns, and are in same color coordinate.
, with the power of control beam IC to be 0.58I0. This XNOR logic gate shows a high intensity contrast of the output states “1” and “0” as about 16dB.

4. Conclusion

In this paper, we realize the whole set of fundamental logic operations in devices formed by metal slot waveguides. We show a single Y-shaped waveguide junction can work as AND, OR, NOT and XOR logic gates. By using two cascaded Y-shaped junction, with one port for control signal, NAND, NOR and XNOR gates can be realized. The working principle is discussed in detail and the working efficiency is verified by electromagnetic simulations. The metal slot waveguide based logic gates show small sizes and high intensity contrasts for the output states “1” and “0”. Assembles of these gates can realize more complicated functions and construct future optical computing chip.

Acknowledgments

This work was supported by MOST Grants (No. 2009CB930700), NSFC Grants (Nos. 11004237, 11134013, 11227407) and “Knowledge Innovation Project” (KJCX2-EW-W04) of CAS.

References and links

1.

H. J. Caulfield and S. Dolev, “Why future supercomputing requires optics,” Nat. Photonics 4(5), 261–263 (2010). [CrossRef]

2.

H. J. Caulfield and J. Westphal, “The logic of optics and the optics of logic,” Inf. Sci. 162(1), 21–33 (2004). [CrossRef]

3.

L. Qian and H. J. Caulfield, “What can we do with a linear optical logic gate?” Inf. Sci. 176(22), 3379–3392 (2006). [CrossRef]

4.

Y. Zhang, Y. Zhang, and B. Li, “Optical switches and logic gates based on self-collimated beams in two-dimensional photonic crystals,” Opt. Express 15(15), 9287–9292 (2007). [CrossRef] [PubMed]

5.

V. R. Almeida, C. A. Barrios, R. R. Panepucci, and M. Lipson, “All-optical control of light on a silicon chip,” Nature 431(7012), 1081–1084 (2004). [CrossRef] [PubMed]

6.

Q. Xu and M. Lipson, “All-optical logic based on silicon micro-ring resonators,” Opt. Express 15(3), 924–929 (2007). [CrossRef] [PubMed]

7.

T. Holmgaard and S. I. Bozhevolnyi, “Theoretical analysis of dielectric-loaded surface plasmon-polariton waveguides,” Phys. Rev. B 75(24), 245405 (2007). [CrossRef]

8.

G. Veronis and S. Fan, “Guided subwavelength plasmonic mode supported by a slot in a thin metal film,” Opt. Lett. 30(24), 3359–3361 (2005). [CrossRef] [PubMed]

9.

S. I. Bozhevolnyi, V. S. Volkov, E. Devaux, and T. W. Ebbesen, “Channel plasmon-polariton guiding by subwavelength metal grooves,” Phys. Rev. Lett. 95(4), 046802 (2005). [CrossRef] [PubMed]

10.

R. M. Dickson and L. A. Lyon, “Unidirectional Plasmon Propagation in Metallic Nanowires,” J. Phys. Chem. B 104(26), 6095–6098 (2000). [CrossRef]

11.

A. V. Krasavin and A. V. Zayats, “Passive photonic elements based on dielectric-loaded surface plasmon polariton waveguides,” Appl. Phys. Lett. 90(21), 211101 (2007). [CrossRef]

12.

S. I. Bozhevolnyi, V. S. Volkov, E. Devaux, J. Y. Laluet, and T. W. Ebbesen, “Channel plasmon subwavelength waveguide components including interferometers and ring resonators,” Nature 440(7083), 508–511 (2006). [CrossRef] [PubMed]

13.

G. Veronis and S. Fan, “Bends and splitters in metal-dielectirc-metal subwavelength plasmonic waveguides,” Appl. Phys. Lett. 87(13), 131102 (2005). [CrossRef]

14.

Y. Fang, Z. Li, Y. Huang, S. Zhang, P. Nordlander, N. J. Halas, and H. Xu, “Branched Silver Nanowires as Controllable Plasmon Routers,” Nano Lett. 10(5), 1950–1954 (2010). [CrossRef] [PubMed]

15.

H. Wei, Z. Li, X. Tian, Z. Wang, F. Cong, N. Liu, S. Zhang, P. Nordlander, N. J. Halas, and H. Xu, “Quantum Dot-Based Local Field Imaging Reveals Plasmon-Based Interferometric Logic in Silver Nanowire Networks,” Nano Lett. 11(2), 471–475 (2011). [CrossRef] [PubMed]

16.

H. Wei, Z. Wang, X. Tian, M. Käll, and H. Xu, “Cascaded logic gates in nanophotonic plasmon networks,” Nat Commun 2, 387 (2011). [CrossRef] [PubMed]

17.

Y. Fu, X. Hu, C. Lu, S. Yue, H. Yang, and Q. Gong, “All-Optical Logic Gates Based on Nanoscale Plasmonic Slot Waveguides,” Nano Lett. 12(11), 5784–5790 (2012). [CrossRef] [PubMed]

18.

P. B. Johnson and R. W. Christy, “Optical constants of the noble metals,” Phys. Rev. B 6(12), 4370–4379 (1972). [CrossRef]

OCIS Codes
(200.4660) Optics in computing : Optical logic
(230.7370) Optical devices : Waveguides
(250.5403) Optoelectronics : Plasmonics

ToC Category:
Optics in Computing

History
Original Manuscript: January 24, 2013
Revised Manuscript: March 13, 2013
Manuscript Accepted: March 13, 2013
Published: April 10, 2013

Citation
Deng Pan, Hong Wei, and Hongxing Xu, "Optical interferometric logic gates based on metal slot waveguide network realizing whole fundamental logic operations," Opt. Express 21, 9556-9562 (2013)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-21-8-9556


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References

  1. H. J. Caulfield and S. Dolev, “Why future supercomputing requires optics,” Nat. Photonics4(5), 261–263 (2010). [CrossRef]
  2. H. J. Caulfield and J. Westphal, “The logic of optics and the optics of logic,” Inf. Sci.162(1), 21–33 (2004). [CrossRef]
  3. L. Qian and H. J. Caulfield, “What can we do with a linear optical logic gate?” Inf. Sci.176(22), 3379–3392 (2006). [CrossRef]
  4. Y. Zhang, Y. Zhang, and B. Li, “Optical switches and logic gates based on self-collimated beams in two-dimensional photonic crystals,” Opt. Express15(15), 9287–9292 (2007). [CrossRef] [PubMed]
  5. V. R. Almeida, C. A. Barrios, R. R. Panepucci, and M. Lipson, “All-optical control of light on a silicon chip,” Nature431(7012), 1081–1084 (2004). [CrossRef] [PubMed]
  6. Q. Xu and M. Lipson, “All-optical logic based on silicon micro-ring resonators,” Opt. Express15(3), 924–929 (2007). [CrossRef] [PubMed]
  7. T. Holmgaard and S. I. Bozhevolnyi, “Theoretical analysis of dielectric-loaded surface plasmon-polariton waveguides,” Phys. Rev. B75(24), 245405 (2007). [CrossRef]
  8. G. Veronis and S. Fan, “Guided subwavelength plasmonic mode supported by a slot in a thin metal film,” Opt. Lett.30(24), 3359–3361 (2005). [CrossRef] [PubMed]
  9. S. I. Bozhevolnyi, V. S. Volkov, E. Devaux, and T. W. Ebbesen, “Channel plasmon-polariton guiding by subwavelength metal grooves,” Phys. Rev. Lett.95(4), 046802 (2005). [CrossRef] [PubMed]
  10. R. M. Dickson and L. A. Lyon, “Unidirectional Plasmon Propagation in Metallic Nanowires,” J. Phys. Chem. B104(26), 6095–6098 (2000). [CrossRef]
  11. A. V. Krasavin and A. V. Zayats, “Passive photonic elements based on dielectric-loaded surface plasmon polariton waveguides,” Appl. Phys. Lett.90(21), 211101 (2007). [CrossRef]
  12. S. I. Bozhevolnyi, V. S. Volkov, E. Devaux, J. Y. Laluet, and T. W. Ebbesen, “Channel plasmon subwavelength waveguide components including interferometers and ring resonators,” Nature440(7083), 508–511 (2006). [CrossRef] [PubMed]
  13. G. Veronis and S. Fan, “Bends and splitters in metal-dielectirc-metal subwavelength plasmonic waveguides,” Appl. Phys. Lett.87(13), 131102 (2005). [CrossRef]
  14. Y. Fang, Z. Li, Y. Huang, S. Zhang, P. Nordlander, N. J. Halas, and H. Xu, “Branched Silver Nanowires as Controllable Plasmon Routers,” Nano Lett.10(5), 1950–1954 (2010). [CrossRef] [PubMed]
  15. H. Wei, Z. Li, X. Tian, Z. Wang, F. Cong, N. Liu, S. Zhang, P. Nordlander, N. J. Halas, and H. Xu, “Quantum Dot-Based Local Field Imaging Reveals Plasmon-Based Interferometric Logic in Silver Nanowire Networks,” Nano Lett.11(2), 471–475 (2011). [CrossRef] [PubMed]
  16. H. Wei, Z. Wang, X. Tian, M. Käll, and H. Xu, “Cascaded logic gates in nanophotonic plasmon networks,” Nat Commun2, 387 (2011). [CrossRef] [PubMed]
  17. Y. Fu, X. Hu, C. Lu, S. Yue, H. Yang, and Q. Gong, “All-Optical Logic Gates Based on Nanoscale Plasmonic Slot Waveguides,” Nano Lett.12(11), 5784–5790 (2012). [CrossRef] [PubMed]
  18. P. B. Johnson and R. W. Christy, “Optical constants of the noble metals,” Phys. Rev. B6(12), 4370–4379 (1972). [CrossRef]

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