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Optics Express

Optics Express

  • Editor: Andrew M. Weiner
  • Vol. 21, Iss. 9 — May. 6, 2013
  • pp: 10962–10968
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30-Gb/s 90-nm CMOS-driven equalized multimode optical link

Brendan H. Hamel-Bissell, Jonathan E. Proesel, Benjamin G. Lee, Daniel M. Kuchta, Alexander V. Rylyakov, and Clint L. Schow  »View Author Affiliations


Optics Express, Vol. 21, Issue 9, pp. 10962-10968 (2013)
http://dx.doi.org/10.1364/OE.21.010962


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Abstract

Abstract: We report an 850-nm vertical cavity surface emitting laser (VCSEL)-based optical link that achieves a new record in speed. The laser driver and receiver ICs are fabricated in standard 90-nm bulk CMOS, and the optoelectronic devices are commercial components. Operation at 30 Gb/s with a bit-error rate < 10−12 is achieved, representing to the authors’ knowledge the highest speed reported to date for a CMOS-based full optical link. Transmitter feed-forward equalization is shown to improve maximum data rate from 25 to 30 Gb/s, timing margin by 17% at 23.5 Gb/s, and receiver sensitivity by 4 dB at 23.5 Gb/s.

© 2013 OSA

1. Introduction

The size and numerical aperture of MMF cores match well to a VCSEL’s output. Coupling can be accomplished using passive alignment and simple injection molded optics, which reduces production costs. The fiber’s bandwidth is sufficient for short reach links. Assuming launch conditions that meet the encircled flux standards, OM2 fiber is characterized to support a minimum of 500 MHz-km, which can support 10 Gb/s Ethernet over an 82 m link. More recent OM4 fiber has the same 50 µm core diameter, but has an effective bandwidth of 4700 MHz-km to support 100 Gb/s over 125 m [4

4. A. Nielsen, “AMP NETCONNECT Guide to ISO/IEC 11801 2nd Edition Including Amendment 1,” http://www.lanster.com/pub/files/file/okablowanie_normy/Guide_ISO_11801_2nd_Amendment1.pdf.

].

2. Optical link design

The optical link is shown in Fig. 1(a)
Fig. 1 (a) Optical link block diagram, (b) Feed-forward equalization waveform (from [4]). (c) Photograph of transmitter IC and VCSELs mounted on high-speed PCB, (d) Photograph of receiver IC and photodiode mounted on high-speed PCB.
. The transmitter consists of a two-stage current-mode-logic (CML) differential pre-amplifier followed by split main and post cursor paths as reported in [3

3. J. E. Proesel, B. G. Lee, A. V. Rylyakov, C. W. Baks, and C. L. Schow, “Ultra low power 10- to 28.5-Gb/s CMOS-driven VCSEL-based optical links,” J. Opt. Commun. Netw. 4(11), B114–B123 (2012). [CrossRef]

]. The post-cursor path uses a chain of amplifiers to act as a delay, which are followed by the post-cursor tap driver. The main cursor is buffered by a single amplifier before the main cursor driver. All amplifiers are differential current mode logic (CML) stages with inductive peaking for bandwidth extension. The VCSEL, which is fabricated by Emcore for 20 to 25 Gb/s operation, has a 7.5 µm aperture, sub-mA threshold, and 0.41 W/A slope efficiency. Two VCSELs are wirebonded to the transmitter chip, one outputting the optical signal and the other acting as a dummy load. The power consumption of the dummy VCSEL is not counted in the power efficiencies reported here since in a product design, the dummy load VCSEL would be straightforwardly replaced by an on-chip resistive load or omitted entirely to save power.

The effect of separating and recombining the post-cursor and main cursor paths is shown in Fig. 1(b). An adjustable delay bias varies the delay time caused by the chain of amplifiers. This combined with the adjustable post and main cursor tap weight causes the FFE output to act as a summation of the input signal with a delayed and an inverted copy of itself as shown in Fig. 1(b). The output of the FFE caries the same information as the input in a waveform with peaked rising and falling edges and a reduced DC swing. This emphasizes the high frequency portion of the waveform and can lead to improvements in bandwidth restricted components such as the VCSEL, MMF, photodiode (PD), transimpedance amplifier (TIA), and limiting amplifier (LA) [8

8. A. V. Rylyakov, C. L. Schow, B. G. Lee, F. E. Doany, C. W. Baks, and J. A. Kash, “Transmitter predistortion for simultaneous improvements in bit rate, sensitivity, jitter, and power efficiency in 20 Gb/s CMOS-driven VCSEL links,” J. Lightwave Technol. 30(4), 399–405 (2012). [CrossRef]

].

The block diagram of the receiver IC is shown in Fig. 1(a). The receiver takes a differential ac-coupled signal into a transimpedance amplifier followed by six Cherry-Hooper stages and a CML output buffer to drive ac-coupled 50 Ω off-chip loads. The receiver transimpedance gain is approximately 12 kΩ at nominal supply voltages. The photodiode is also fabricated by Emcore with a 25 µm diameter. Both the transmitter and receiver ICs are fabricated in IBM’s standard bulk 90 nm CMOS process.

3. Optical link measurement results

The transmitter IC and VCSELs are mounted on a custom high-speed printed circuit board and the receiver IC and photodiode are mounted on separate board for testing. The TX and RX assemblies are shown in Figs. 1(c) and 1(d), where it is clear that the area of both ICs are pad limited and the high-speed circuitry occupies a small fraction of the chip footprint. In the TX chip, the main and post-cursor amplifier stages are highlighted, with the equalizer circuitry occupying ~40% of the total circuit area. The transmitter and receiver are joined by 4 m (2 + 2 m lengths) of OM2 MMF using lensed 50 µm MMF probes to couple emission from the VCSEL and to focus onto the photodiode. The coupling efficiency on the TX side is ~80%, and close to 100% on the RX side. A 30 GHz bandwidth sampling oscilloscope is used for electrical receiver output eye diagram measurements and a 17 GHz bandwidth Newport D-25xr photodiode is used to capture transmitter optical eye diagrams.

Table 1

Table 1. Power consumption (mW) for supplies shown in Fig. 1.

table-icon
View This Table
shows the power consumption for the various supplies indicated in Fig. 1(a). The limiting amplifier consumes most of the power, and cannot be reduced at data rates below 20 Gb/s without sacrificing the receiver output amplitude. The link’s bandwidth limitations make it less efficient at higher bit rates since the supply voltages must be increased to gain more bandwidth. Nearly 150 mW must be added to increase from 20 Gb/s to 30 Gb/s, while only 14 mW is needed to increase from 10 Gb/s to 20 Gb/s. Figure 3 also shows the effect of equalization on power efficiency. The measurement procedure is the same as above; however, the link is optimized at each data rate with post-cursor DELAY and TAP grounded, disabling the equalization. Without equalization, the maximum achievable bit rate is 25 Gb/s and the best power efficiency is 3.48 pJ/bit at 18 Gb/s. At 14 Gb/s, the curves begin to converge indicating that the link is no longer bandwidth limited and there is no performance improvement with equalization enabled.

4. Conclusion

Acknowledgments

The authors would like to thank M. Taubenblatt for management support, and Sumitomo Electric Device Innovations USA (formerly Emcore) for the VCSELs and PDs. The authors gratefully acknowledge support from DARPA under contract MDA972-03-3-0004. The views, opinions, and/or findings contained in this article are those of the authors and should not be interpreted as representing the official views or policies, either expressed or implied, of DARPA or the Department of Defense. Approved for Public Release, Distribution Unlimited.

References

1.

J. A. Kash, A. F. Benner, F. E. Doany, D. M. Kuchta, B. G. Lee, K. Petar, L. Schares, C. L. Schow, and M. Taubenblatt, “Optical interconnects in future servers,” in Proc. of Optical Fiber Communications Conference (IEEE, 2011), paper OTuH1. [CrossRef]

2.

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. Block, M. R. Reshotko, and P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid-State Circuits 45(1), 235–248 (2010). [CrossRef]

3.

J. E. Proesel, B. G. Lee, A. V. Rylyakov, C. W. Baks, and C. L. Schow, “Ultra low power 10- to 28.5-Gb/s CMOS-driven VCSEL-based optical links,” J. Opt. Commun. Netw. 4(11), B114–B123 (2012). [CrossRef]

4.

A. Nielsen, “AMP NETCONNECT Guide to ISO/IEC 11801 2nd Edition Including Amendment 1,” http://www.lanster.com/pub/files/file/okablowanie_normy/Guide_ISO_11801_2nd_Amendment1.pdf.

5.

C. L. Schow, A. V. Rylyakov, C. Baks, F. E. Doany, and J. A. Kash, “25-Gb/s 6.5-pJ/bit 90-nm CMOS-driven multimode optical link,” IEEE Photon. Technol. Lett. 24(10), 824–826 (2012). [CrossRef]

6.

S. Palermo, A. Emami-Neyestanak, and M. Horowitz, “A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects,” in 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (IEEE, 2007), pp. 44–586. [CrossRef]

7.

A. Kern, A. Chandrakasan, and I. Young, “18Gb/s Optical IO: VCSEL Driver and TIA in 90nm CMOS,” in 2007 IEEE Symposium on VLSI Circuits (IEEE, 2007), pp. 276–277. [CrossRef]

8.

A. V. Rylyakov, C. L. Schow, B. G. Lee, F. E. Doany, C. W. Baks, and J. A. Kash, “Transmitter predistortion for simultaneous improvements in bit rate, sensitivity, jitter, and power efficiency in 20 Gb/s CMOS-driven VCSEL links,” J. Lightwave Technol. 30(4), 399–405 (2012). [CrossRef]

9.

D. M. Kuchta, A. V. Rylyakov, C. L. Schow, J. E. Proesel, C. Baks, C. Kocot, L. Graham, R. Johnson, G. Landry, E. Shaw, A. MacInnes, and J. Tatum, “55Gb/s Directly Modulated 850nm VCSEL-Based Optical Link”, in Proc. of IEEE Photonics Conference (IEEE, 2012), paper PD1.5. [CrossRef]

10.

B. Kögel, J. S. Gustavsson, E. Haglund, R. Safaisini, A. Joel, P. Westbergh, M. Geen, R. Lawrence, and A. Larsson, “High-speed 850 nm VCSELs with 28 GHz modulation bandwidth operating error-free up to 44 Gbit/s,” Electron. Lett. 48(18), 1145–1147 (2012). [CrossRef]

11.

P. Wolf, P. Moser, G. Larisch, M. Kroh, A. Mutig, W. Unrau, W. Hofmann, and D. Bimberg, “High-performance 980 nm VCSELs for 12.5 Gbit/s data transmission at 155 degrees C and 49 Gbit/s at-14 degrees C,” Electron. Lett. 48(7), 389–390 (2012). [CrossRef]

12.

N. Suzuki, H. Hatakeyama, K. Yashiki, K. Fukatsu, K. Tokutome, T. Akagawa, T. Anan, and M. Tsuji, “High-speed InGaAs VCSELs,” Proc. of 19th Annual Meeting of the IEEE Lasers and Electro-Optics Society (IEEE, 2006), pp.508–509. [CrossRef]

13.

W. Hofmann, M. Müller, P. Wolf, A. Mutig, T. Gründl, G. Böhm, D. Bimberg, and M.-C. Amann, “40 Gbit/s modulation of 1550 nm VCSEL,” Electron. Lett. 47(4), 270–271 (2011). [CrossRef]

OCIS Codes
(200.4650) Optics in computing : Optical interconnects
(250.7260) Optoelectronics : Vertical cavity surface emitting lasers

ToC Category:
Optoelectronics

History
Original Manuscript: February 4, 2013
Revised Manuscript: April 16, 2013
Manuscript Accepted: April 17, 2013
Published: April 26, 2013

Citation
Brendan H. Hamel-Bissell, Jonathan E. Proesel, Benjamin G. Lee, Daniel M. Kuchta, Alexander V. Rylyakov, and Clint L. Schow, "30-Gb/s 90-nm CMOS-driven equalized multimode optical link," Opt. Express 21, 10962-10968 (2013)
http://www.opticsinfobase.org/oe/abstract.cfm?URI=oe-21-9-10962


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References

  1. J. A. Kash, A. F. Benner, F. E. Doany, D. M. Kuchta, B. G. Lee, K. Petar, L. Schares, C. L. Schow, and M. Taubenblatt, “Optical interconnects in future servers,” in Proc. of Optical Fiber Communications Conference (IEEE, 2011), paper OTuH1. [CrossRef]
  2. I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. Block, M. R. Reshotko, and P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid-State Circuits45(1), 235–248 (2010). [CrossRef]
  3. J. E. Proesel, B. G. Lee, A. V. Rylyakov, C. W. Baks, and C. L. Schow, “Ultra low power 10- to 28.5-Gb/s CMOS-driven VCSEL-based optical links,” J. Opt. Commun. Netw.4(11), B114–B123 (2012). [CrossRef]
  4. A. Nielsen, “AMP NETCONNECT Guide to ISO/IEC 11801 2nd Edition Including Amendment 1,” http://www.lanster.com/pub/files/file/okablowanie_normy/Guide_ISO_11801_2nd_Amendment1.pdf .
  5. C. L. Schow, A. V. Rylyakov, C. Baks, F. E. Doany, and J. A. Kash, “25-Gb/s 6.5-pJ/bit 90-nm CMOS-driven multimode optical link,” IEEE Photon. Technol. Lett.24(10), 824–826 (2012). [CrossRef]
  6. S. Palermo, A. Emami-Neyestanak, and M. Horowitz, “A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects,” in 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (IEEE, 2007), pp. 44–586. [CrossRef]
  7. A. Kern, A. Chandrakasan, and I. Young, “18Gb/s Optical IO: VCSEL Driver and TIA in 90nm CMOS,” in 2007 IEEE Symposium on VLSI Circuits (IEEE, 2007), pp. 276–277. [CrossRef]
  8. A. V. Rylyakov, C. L. Schow, B. G. Lee, F. E. Doany, C. W. Baks, and J. A. Kash, “Transmitter predistortion for simultaneous improvements in bit rate, sensitivity, jitter, and power efficiency in 20 Gb/s CMOS-driven VCSEL links,” J. Lightwave Technol.30(4), 399–405 (2012). [CrossRef]
  9. D. M. Kuchta, A. V. Rylyakov, C. L. Schow, J. E. Proesel, C. Baks, C. Kocot, L. Graham, R. Johnson, G. Landry, E. Shaw, A. MacInnes, and J. Tatum, “55Gb/s Directly Modulated 850nm VCSEL-Based Optical Link”, in Proc. of IEEE Photonics Conference (IEEE, 2012), paper PD1.5. [CrossRef]
  10. B. Kögel, J. S. Gustavsson, E. Haglund, R. Safaisini, A. Joel, P. Westbergh, M. Geen, R. Lawrence, and A. Larsson, “High-speed 850 nm VCSELs with 28 GHz modulation bandwidth operating error-free up to 44 Gbit/s,” Electron. Lett.48(18), 1145–1147 (2012). [CrossRef]
  11. P. Wolf, P. Moser, G. Larisch, M. Kroh, A. Mutig, W. Unrau, W. Hofmann, and D. Bimberg, “High-performance 980 nm VCSELs for 12.5 Gbit/s data transmission at 155 degrees C and 49 Gbit/s at-14 degrees C,” Electron. Lett.48(7), 389–390 (2012). [CrossRef]
  12. N. Suzuki, H. Hatakeyama, K. Yashiki, K. Fukatsu, K. Tokutome, T. Akagawa, T. Anan, and M. Tsuji, “High-speed InGaAs VCSELs,” Proc. of 19th Annual Meeting of the IEEE Lasers and Electro-Optics Society (IEEE, 2006), pp.508–509. [CrossRef]
  13. W. Hofmann, M. Müller, P. Wolf, A. Mutig, T. Gründl, G. Böhm, D. Bimberg, and M.-C. Amann, “40 Gbit/s modulation of 1550 nm VCSEL,” Electron. Lett.47(4), 270–271 (2011). [CrossRef]

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