Architectural and performance considerations for a 107-instruction/sec optoelectronic central processing unit
Optics Letters, Vol. 12, Issue 11, pp. 956-958 (1987)
http://dx.doi.org/10.1364/OL.12.000956
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Abstract
Architectural considerations for a multiple-instruction, single-data-based optoelectronic central processing unit operating at 107 instructions per second are detailed. Central to the operation of this device is a giant fiber-optic content-addressable memory in a programmable logic array configuration. The design includes four instructions and emphasizes the fan-in and fan-out capabilities of optical systems. Interconnection limitations and scaling issues are examined.
© 1987 Optical Society of America
Citation
R. Arrathoon and S. Kozaitis, "Architectural and performance considerations for a 107-instruction/sec optoelectronic central processing unit," Opt. Lett. 12, 956-958 (1987)
http://www.opticsinfobase.org/ol/abstract.cfm?URI=ol-12-11-956
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