Architectural considerations for a multiple-instruction, single-data-based optoelectronic central processing unit operating at 107 instructions per second are detailed. Central to the operation of this device is a giant fiber-optic content-addressable memory in a programmable logic array configuration. The design includes four instructions and emphasizes the fan-in and fan-out capabilities of optical systems. Interconnection limitations and scaling issues are examined.
© 1987 Optical Society of America
R. Arrathoon and S. Kozaitis, "Architectural and performance considerations for a 107-instruction/sec optoelectronic central processing unit," Opt. Lett. 12, 956-958 (1987)