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Optical Materials Express

Optical Materials Express

  • Editor: David J. Hagan
  • Vol. 2, Iss. 10 — Oct. 1, 2012
  • pp: 1336–1342
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Selective area growth of germanium and germanium/silicon-germanium quantum wells in silicon waveguides for on-chip optical interconnect applications

S. A. Claussen, K. C. Balram, E. T. Fei, T. I. Kamins, J. S. Harris, and D. A. B. Miller  »View Author Affiliations


Optical Materials Express, Vol. 2, Issue 10, pp. 1336-1342 (2012)
http://dx.doi.org/10.1364/OME.2.001336


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Abstract

We propose a robust fabrication process for growing Ge and Ge-based heterostructures in growth windows with Si sidewalls which can be applied to growth in thick Si optical waveguides. Sidewall growth is eliminated by the presence of a dielectric spacer layer which covers the sidewalls. We demonstrate the effectiveness of this process by selective-area growth of Ge and Ge/SiGe quantum wells, and show an improved performance and increased process reliability over previous work.

© 2012 OSA

1. Introduction

The ability to selectively grow germanium in specific regions of a silicon substrate is highly desirable for the future integration of Ge-based optoelectronice devices with high-speed Si-based electronic circuits. Potential applications include dense integration of high-performance photodetectors [1

1. J. Michel, J. Liu, and L. C. Kimerling, “High-performance Ge-on-Si photodetectors,” Nat. Photonics 4(8), 527–534 (2010). [CrossRef]

,2

2. M. Kim, O. O. Olubuyide, J. U. Yoon, and J. L. Hoyt, “Selective epitaxial growth of Ge-on-Si for photodiode applications,” ECS Trans. 16, 837–847 (2008). [CrossRef]

] and optical modulators [3

3. S. Ren, Y. Rong, S. A. Claussen, R. K. Schaevitz, T. I. Kamins, J. S. Harris, and D. A. B. Miller, “Ge/SiGe quantum well waveguide modulator monolithically integrated with SOI waveguides,” IEEE Photon. Technol. Lett. 24(6), 461–463 (2012). [CrossRef]

,4

4. N. N. Feng, S. Liao, D. Feng, X. Wang, P. Dong, H. Liang, C. C. Kung, W. Qian, Y. Liu, J. Fong, R. Shafiiha, Y. Luo, J. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “Design and fabrication of 3μm silicon-on-insulator waveguide integrated Ge electro-absorption modulator,” Opt. Express 19(9), 8715–8720 (2011). [CrossRef] [PubMed]

]. While selective-area growth of Ge has been investigated since the mid-1980s [5

5. H. Ishii, Y. Takahashi, and J. Murota, “Selective Ge deposition on Si using thermal decomposition of GeH4,” Appl. Phys. Lett. 47(8), 863–865 (1985). [CrossRef]

], using these growth processes in the fabrication of actual devices often introduces additional challenges. For example, selective growth of Ge is commonly carried out by using a dielectric mask such as silicon dioxide (SiO2) or silicon nitride (Si3N4) above the Si substrate. Growth windows are etched through the dielectric and Ge growth is initiated at the exposed Si surface [1

1. J. Michel, J. Liu, and L. C. Kimerling, “High-performance Ge-on-Si photodetectors,” Nat. Photonics 4(8), 527–534 (2010). [CrossRef]

,6

6. S. Ren, Y. Rong, T. I. Kamins, J. S. Harris, and D. A. B. Miller, “Selective epitaxial growth of Ge/Si0.15Ge0.85 quantum wells on Si substrate using reduced pressure chemical vapor deposition,” Appl. Phys. Lett. 98(15), 151108 (2011). [CrossRef]

]. Certain device designs [3

3. S. Ren, Y. Rong, S. A. Claussen, R. K. Schaevitz, T. I. Kamins, J. S. Harris, and D. A. B. Miller, “Ge/SiGe quantum well waveguide modulator monolithically integrated with SOI waveguides,” IEEE Photon. Technol. Lett. 24(6), 461–463 (2012). [CrossRef]

,4

4. N. N. Feng, S. Liao, D. Feng, X. Wang, P. Dong, H. Liang, C. C. Kung, W. Qian, Y. Liu, J. Fong, R. Shafiiha, Y. Luo, J. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “Design and fabrication of 3μm silicon-on-insulator waveguide integrated Ge electro-absorption modulator,” Opt. Express 19(9), 8715–8720 (2011). [CrossRef] [PubMed]

] require growth of a Ge region inside a Si optical waveguide, with the growth regions etched through the dielectric layer and into the underlying Si waveguide layer. Since any exposed crystalline silicon surface can serve as a growth template for the Ge, the exposed Si sidewalls initiate deleterious growth that affects both the optical and electronic properties of the device. In this work, we propose and demonstrate a fabrication process to reliably prevent growth on these Si sidewalls, even in relatively thick structures, and demonstrate highly selective growth of both Ge and SiGe.

Ge and Ge/SiGe quantum wells (QWs) both exhibit electroabsorption effects (the Franz-Keldysh effect in bulk Ge [7

7. W. Franz, “Influence of an electric field on an optical absorption edge,” Z. Naturforsch. B 13a, 484–489 (1958).

,8

8. L. V. Keldysh, “The effect of a strong electric field on the optical properties of insulating crystals,” Sov. Phys. JETP 7, 788–790 (1958).

] and the quantum confined Stark effect (QCSE) in Ge/SiGe QWs [9

9. Y. H. Kuo, Y. K. Lee, Y. Ge, S. Ren, J. E. Roth, T. I. Kamins, D. A. B. Miller, and J. S. Harris, “Strong quantum-confined Stark effect in germanium quantum-well structures on silicon,” Nature 437(7063), 1334–1336 (2005). [CrossRef] [PubMed]

]), where an increase in the applied electric field redshifts the absorption spectrum of the material. This behavior allows the development of compact, high-performance, Ge-based Si-compatible optical modulators for optical interconnect applications [10

10. D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009). [CrossRef]

,11

11. G. T. Reed, G. Mashanovich, F. Y. Gardes, and D. J. Thomson, “Silicon optical modulators,” Nat. Photonics 4(8), 518–526 (2010). [CrossRef]

]. Waveguide-based modulators allow for longer interaction lengths between the optical beam and the active material and easier integration with other on-chip optical components. However, to minimize loss from background absorption in Ge structures, the modulator region must be integrated with low-loss entrance and exit waveguides, such as silicon-on-insulator (SOI) waveguides. These waveguides can be single-mode while still being relatively thick. Coupling between the active Ge region and the passive waveguide can be carried out either evanescently using adiabatic tapers [12

12. N. N. Feng, P. Dong, D. Zheng, S. Liao, H. Liang, R. Shafiiha, D. Feng, G. Li, J. E. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “Vertical p-i-n germanium photodetector with high external responsivity integrated with large core Si waveguides,” Opt. Express 18(1), 96–101 (2010). [CrossRef] [PubMed]

] or through direct butt coupling [3

3. S. Ren, Y. Rong, S. A. Claussen, R. K. Schaevitz, T. I. Kamins, J. S. Harris, and D. A. B. Miller, “Ge/SiGe quantum well waveguide modulator monolithically integrated with SOI waveguides,” IEEE Photon. Technol. Lett. 24(6), 461–463 (2012). [CrossRef]

]. In the case of adiabatic coupling, a Ge layer is grown directly above the Si layer of the SOI substrate. The adiabatic tapers used are typically very long, increasing the footprint of the device and, if formed out of the active Ge material, increasing the device capacitance. Growing the Ge or Ge/SiGe QWs in growth windows directly in the SOI waveguide, butt-coupling the modulation region to the input and output waveguides, enables a modulator with a small footprint and low capacitance. However, these growth windows can have very thick sidewalls of exposed Si (depending on the thickness of the SOI waveguide), where Ge growth is expected to occur if preventative steps are not taken.

This growth on the exposed Si sidewalls needs to be avoided because it can significantly disturb the planarity of the device, making post-growth fabrication and integration with other devices difficult or requiring chemical mechanical polishing (CMP). Planarity is also important for the optimal performance of heterostructures like QWs. Furthermore, for active devices that rely on pn or p-i-n junctions that are doped in situ during growth, growth on the sidewalls can lead to electrical shorting of the device or high leakage current.

2. Design motivation

To prevent sidewall growth and enable high-quality growth in the desired regions, a process was previously proposed to deposit a dielectric spacer on the sidewalls of the growth windows [13

13. S. Ren, T. I. Kamins, and D. A. B. Miller, “Thin dielectric spacer for the monolithic integration of bulk germanium or germanium quantum wells with silicon-on-insulator waveguides,” IEEE Photon. J. 3(4), 739–747 (2011). [CrossRef]

]. Figure 1(a)
Fig. 1 (a) Desired growth results using the substrate preparation process suggested by Ren et al. [13]. (b) Scanning electron microscope (SEM) image of selective area growth of Ge/SiGe QWs. Implementation of the spacer fabrication process proved to be not very robust, and often resulted in undesired sidewall growth originating from the top corner of the Si sidewall, directly under the SiO2 mask edge (circled region). The dielectric spacer was likely removed from this corner during a dry etching step in the substrate fabrication, due to insufficient coverage of the spacer by the top SiO2 mask.
shows a schematic of the designed substrate, with Ge/SiGe QW growth in the growth window of an SOI waveguide. (It should be noted that while much of the discussion here focuses on integration with 3 µm-thick SOI waveguides because this is the desired application, the results transfer completely to applications that require selectively growing in growth windows etched into bulk Si substrates or SOI waveguides of different thicknesses. In fact, much of the development of this work and the results shown here were done using Si substrates.) Unfortunately, while this previously proposed spacer fabrication process did allow the demonstration of high-quality QW growth, it was not robust to minor fabrication variations, making mode-matched growth with SOI waveguides unreliable. Figure 1(b) presents a typical result, with excessive sidewall growth visible and planar QW growth at the center of the growth window. Despite many efforts to modify this fabrication process, it proved to be very sensitive to minor process variations, which led to poor repeatability and yield. A weak point in the approach was determined to be at the top corner of the Si sidewall, directly under the SiO2 growth mask. The dielectric spacer was likely removed from this corner during a dry etching step in the substrate fabrication, if the spacer layer at this corner was not sufficiently protected during the etch by the top SiO2 mask.

To overcome this problem of unreliable spacer fabrication and thus substantial sidewall growth, we propose a change in the original spacer fabrication process set forth by Ren et al. [13

13. S. Ren, T. I. Kamins, and D. A. B. Miller, “Thin dielectric spacer for the monolithic integration of bulk germanium or germanium quantum wells with silicon-on-insulator waveguides,” IEEE Photon. J. 3(4), 739–747 (2011). [CrossRef]

] that renders it independent of process variations. When determining a potential fabrication process for the spacer, a few considerations need to be kept in mind. First, it is desirable to make the spacer as thin as possible, to minimize optical loss [13

13. S. Ren, T. I. Kamins, and D. A. B. Miller, “Thin dielectric spacer for the monolithic integration of bulk germanium or germanium quantum wells with silicon-on-insulator waveguides,” IEEE Photon. J. 3(4), 739–747 (2011). [CrossRef]

]. The spacer needs to also be formed only on the vertical sidewalls of the growth window, not at the bottom of the window, where the epitaxial growth is initiated. Finally, great care needs to be taken so that the spacer fabrication does not damage this growth surface at the bottom of the window.

3. Fabrication process

In our new process, however, following removal of the photoresist, the Si device layer is etched in a wet etchant to undercut the Si sidewalls. Room temperature tetramethylammonium hydroxide (TMAH) was used here. As shown in Fig. 3
Fig. 3 Longer wet etch times of the Si sidewalls lead to greater amounts of undercut, as shown by these cross section SEM images of samples that were etched for (a) 2 minutes, (b) 5 minutes, and (c) 10 minutes. The wet etch used in this work, tetramethylammonium hydroxide, etches different crystal planes of Si at different rates, resulting in the faceting evident at longer etch times.
, the undercut can be controlled by the etch time used. Following this wet etch, the wafer is thermally oxidized to form the SiO2 spacer layer. The simulations by Ren et al. show that optical reflections and scattering off this spacer layer decrease as the thickness of the SiO2 layer decreases [13

13. S. Ren, T. I. Kamins, and D. A. B. Miller, “Thin dielectric spacer for the monolithic integration of bulk germanium or germanium quantum wells with silicon-on-insulator waveguides,” IEEE Photon. J. 3(4), 739–747 (2011). [CrossRef]

]. Thus, the spacer should only be as thick as is necessary for full coverage of the sidewall. In this work, we targeted a final spacer thickness of 80 nm, which Ren et al. predict will transmit about 80% of the optical power [13

13. S. Ren, T. I. Kamins, and D. A. B. Miller, “Thin dielectric spacer for the monolithic integration of bulk germanium or germanium quantum wells with silicon-on-insulator waveguides,” IEEE Photon. J. 3(4), 739–747 (2011). [CrossRef]

]. This thermal oxidation step also serves to remove damage to the Si surface at the bottom of the growth window that may have occurred during dry etching of this region.

4. Epitaxial growth conditions

In this work, both Ge/SiGe quantum well samples and pure Ge samples were epitaxially grown on either a Si(001) substrate or a silicon-on-insulator substrate (with a 3 µm Si device layer and 375 nm buried oxide layer) in an Applied Materials Centura reduced-pressure chemical vapor deposition (RPCVD) reactor. The growth process used GeH4 and SiH4 in a H2 carrier gas at a temperature of 405°C and a system pressure of 40 Torr. No HCl was added to the process gases so selectivity was not optimal. To decrease the defect density and surface roughness, the quantum wells were grown on p-type Si0.12Ge0.88 buffer layers (in situ doped with boron) that underwent high temperature hydrogen annealing; the pure Ge samples also undergo multiple hydrogen anneals for heteroepitaxy (MHAH) [9

9. Y. H. Kuo, Y. K. Lee, Y. Ge, S. Ren, J. E. Roth, T. I. Kamins, D. A. B. Miller, and J. S. Harris, “Strong quantum-confined Stark effect in germanium quantum-well structures on silicon,” Nature 437(7063), 1334–1336 (2005). [CrossRef] [PubMed]

,14

14. A. Nayfeh, C. O. Chui, K. C. Saraswat, and T. Yonehara, “Effects of hydrogen annealing on heteroepitaxial-Ge layers on Si: Surface roughness and electrical quality,” Appl. Phys. Lett. 85(14), 2815–2817 (2004). [CrossRef]

]. To prevent dopant diffusion into the quantum wells, a layer of intrinsic Si0.12Ge0.88 was grown both before and after the quantum well region. The absorbing region consisted of 20 quantum wells which were 15 nm wide with 35 nm barriers and a top capping layer of n-type, arsine-doped Si0.12Ge0.88.

5. Results and conclusion

As shown in Fig. 4
Fig. 4 SEM images of selective-area Ge growth using the dielectric spacer fabrication process in Fig. 2. (a) Angled image of a sample etched in TMAH for 5 minutes. Ge nucleation is evident on the top surface of the SiO2 mask, indicating imperfect selectivity. (b) Cross section SEM showing Ge crystal facets at the edge of the growth window.
, this altered design reliably leads to high-quality Ge growth with minimal sidewall growth. For this result, a 5 minute TMAH wet etch was used, to ensure an adequate undercut of the Si sidewall while not greatly distorting the profile of the interface between the Si waveguide and the Ge modulation region.

Crystal faceting at the sidewalls, which has been observed in other selective-area growth work [1

1. J. Michel, J. Liu, and L. C. Kimerling, “High-performance Ge-on-Si photodetectors,” Nat. Photonics 4(8), 527–534 (2010). [CrossRef]

,6

6. S. Ren, Y. Rong, T. I. Kamins, J. S. Harris, and D. A. B. Miller, “Selective epitaxial growth of Ge/Si0.15Ge0.85 quantum wells on Si substrate using reduced pressure chemical vapor deposition,” Appl. Phys. Lett. 98(15), 151108 (2011). [CrossRef]

], is evident and points to well-controlled and high-quality growth. This faceting is believed to be due to different crystal planes of Ge or SiGe growing at different rates, depending on the growth temperature used [6

6. S. Ren, Y. Rong, T. I. Kamins, J. S. Harris, and D. A. B. Miller, “Selective epitaxial growth of Ge/Si0.15Ge0.85 quantum wells on Si substrate using reduced pressure chemical vapor deposition,” Appl. Phys. Lett. 98(15), 151108 (2011). [CrossRef]

]. Furthermore, the process developed here is simpler than the previously proposed one, with fewer process steps. This fact, combined with the robustness that is built into the process design due to the presence of the overhanging SiO2 masking layer, leads to much higher yields.

In conclusion, we have developed and demonstrated a process for preparing substrates for selective-area epitaxial growth of Ge and Ge/SiGe QWs in growth windows etched into the Si substrate or Si waveguides. This fabrication process results in a thin dielectric layer completely covering the exposed Si sidewalls of the growth region, preventing Ge growth from occurring on the sidewalls and restricting it to only the bottom of the growth window, as desired. This process enables future integrated low-loss, high-performance Ge and Ge/SiGe QW waveguide modulators and photodetectors monolithically integrated with SOI waveguides.

Acknowledgments

This work was supported in part by Oracle under contract HR0011-08-9-0001 between the Government and Oracle. The views, opinions, and/or findings contained in this article are those of the authors and should not be interpreted as representing the official views or policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the Department of Defense. The authors also acknowledge the support of the IFC Focus Center, one of six research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation program. K.C. Balram and E.T. Fei acknowledge the support of a Stanford Graduate Fellowship. Work was performed in part at the Stanford Nanofabrication Facility (a member of the National Nanotechnology Infrastructure Network) which is supported by the National Science Foundation under Grant ECS-9731293, its lab members, and the industrial members of the Stanford Center for Integrated Systems.

References and links

1.

J. Michel, J. Liu, and L. C. Kimerling, “High-performance Ge-on-Si photodetectors,” Nat. Photonics 4(8), 527–534 (2010). [CrossRef]

2.

M. Kim, O. O. Olubuyide, J. U. Yoon, and J. L. Hoyt, “Selective epitaxial growth of Ge-on-Si for photodiode applications,” ECS Trans. 16, 837–847 (2008). [CrossRef]

3.

S. Ren, Y. Rong, S. A. Claussen, R. K. Schaevitz, T. I. Kamins, J. S. Harris, and D. A. B. Miller, “Ge/SiGe quantum well waveguide modulator monolithically integrated with SOI waveguides,” IEEE Photon. Technol. Lett. 24(6), 461–463 (2012). [CrossRef]

4.

N. N. Feng, S. Liao, D. Feng, X. Wang, P. Dong, H. Liang, C. C. Kung, W. Qian, Y. Liu, J. Fong, R. Shafiiha, Y. Luo, J. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “Design and fabrication of 3μm silicon-on-insulator waveguide integrated Ge electro-absorption modulator,” Opt. Express 19(9), 8715–8720 (2011). [CrossRef] [PubMed]

5.

H. Ishii, Y. Takahashi, and J. Murota, “Selective Ge deposition on Si using thermal decomposition of GeH4,” Appl. Phys. Lett. 47(8), 863–865 (1985). [CrossRef]

6.

S. Ren, Y. Rong, T. I. Kamins, J. S. Harris, and D. A. B. Miller, “Selective epitaxial growth of Ge/Si0.15Ge0.85 quantum wells on Si substrate using reduced pressure chemical vapor deposition,” Appl. Phys. Lett. 98(15), 151108 (2011). [CrossRef]

7.

W. Franz, “Influence of an electric field on an optical absorption edge,” Z. Naturforsch. B 13a, 484–489 (1958).

8.

L. V. Keldysh, “The effect of a strong electric field on the optical properties of insulating crystals,” Sov. Phys. JETP 7, 788–790 (1958).

9.

Y. H. Kuo, Y. K. Lee, Y. Ge, S. Ren, J. E. Roth, T. I. Kamins, D. A. B. Miller, and J. S. Harris, “Strong quantum-confined Stark effect in germanium quantum-well structures on silicon,” Nature 437(7063), 1334–1336 (2005). [CrossRef] [PubMed]

10.

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009). [CrossRef]

11.

G. T. Reed, G. Mashanovich, F. Y. Gardes, and D. J. Thomson, “Silicon optical modulators,” Nat. Photonics 4(8), 518–526 (2010). [CrossRef]

12.

N. N. Feng, P. Dong, D. Zheng, S. Liao, H. Liang, R. Shafiiha, D. Feng, G. Li, J. E. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “Vertical p-i-n germanium photodetector with high external responsivity integrated with large core Si waveguides,” Opt. Express 18(1), 96–101 (2010). [CrossRef] [PubMed]

13.

S. Ren, T. I. Kamins, and D. A. B. Miller, “Thin dielectric spacer for the monolithic integration of bulk germanium or germanium quantum wells with silicon-on-insulator waveguides,” IEEE Photon. J. 3(4), 739–747 (2011). [CrossRef]

14.

A. Nayfeh, C. O. Chui, K. C. Saraswat, and T. Yonehara, “Effects of hydrogen annealing on heteroepitaxial-Ge layers on Si: Surface roughness and electrical quality,” Appl. Phys. Lett. 85(14), 2815–2817 (2004). [CrossRef]

OCIS Codes
(130.3130) Integrated optics : Integrated optics materials
(200.4650) Optics in computing : Optical interconnects
(220.0220) Optical design and fabrication : Optical design and fabrication
(230.7370) Optical devices : Waveguides
(250.4110) Optoelectronics : Modulators

ToC Category:
Materials for Integrated Optics

History
Original Manuscript: August 7, 2012
Revised Manuscript: August 24, 2012
Manuscript Accepted: August 24, 2012
Published: August 31, 2012

Citation
S. A. Claussen, K. C. Balram, E. T. Fei, T. I. Kamins, J. S. Harris, and D. A. B. Miller, "Selective area growth of germanium and germanium/silicon-germanium quantum wells in silicon waveguides for on-chip optical interconnect applications," Opt. Mater. Express 2, 1336-1342 (2012)
http://www.opticsinfobase.org/ome/abstract.cfm?URI=ome-2-10-1336


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References

  1. J. Michel, J. Liu, and L. C. Kimerling, “High-performance Ge-on-Si photodetectors,” Nat. Photonics4(8), 527–534 (2010). [CrossRef]
  2. M. Kim, O. O. Olubuyide, J. U. Yoon, and J. L. Hoyt, “Selective epitaxial growth of Ge-on-Si for photodiode applications,” ECS Trans.16, 837–847 (2008). [CrossRef]
  3. S. Ren, Y. Rong, S. A. Claussen, R. K. Schaevitz, T. I. Kamins, J. S. Harris, and D. A. B. Miller, “Ge/SiGe quantum well waveguide modulator monolithically integrated with SOI waveguides,” IEEE Photon. Technol. Lett.24(6), 461–463 (2012). [CrossRef]
  4. N. N. Feng, S. Liao, D. Feng, X. Wang, P. Dong, H. Liang, C. C. Kung, W. Qian, Y. Liu, J. Fong, R. Shafiiha, Y. Luo, J. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “Design and fabrication of 3μm silicon-on-insulator waveguide integrated Ge electro-absorption modulator,” Opt. Express19(9), 8715–8720 (2011). [CrossRef] [PubMed]
  5. H. Ishii, Y. Takahashi, and J. Murota, “Selective Ge deposition on Si using thermal decomposition of GeH4,” Appl. Phys. Lett.47(8), 863–865 (1985). [CrossRef]
  6. S. Ren, Y. Rong, T. I. Kamins, J. S. Harris, and D. A. B. Miller, “Selective epitaxial growth of Ge/Si0.15Ge0.85 quantum wells on Si substrate using reduced pressure chemical vapor deposition,” Appl. Phys. Lett.98(15), 151108 (2011). [CrossRef]
  7. W. Franz, “Influence of an electric field on an optical absorption edge,” Z. Naturforsch. B13a, 484–489 (1958).
  8. L. V. Keldysh, “The effect of a strong electric field on the optical properties of insulating crystals,” Sov. Phys. JETP7, 788–790 (1958).
  9. Y. H. Kuo, Y. K. Lee, Y. Ge, S. Ren, J. E. Roth, T. I. Kamins, D. A. B. Miller, and J. S. Harris, “Strong quantum-confined Stark effect in germanium quantum-well structures on silicon,” Nature437(7063), 1334–1336 (2005). [CrossRef] [PubMed]
  10. D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE97(7), 1166–1185 (2009). [CrossRef]
  11. G. T. Reed, G. Mashanovich, F. Y. Gardes, and D. J. Thomson, “Silicon optical modulators,” Nat. Photonics4(8), 518–526 (2010). [CrossRef]
  12. N. N. Feng, P. Dong, D. Zheng, S. Liao, H. Liang, R. Shafiiha, D. Feng, G. Li, J. E. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “Vertical p-i-n germanium photodetector with high external responsivity integrated with large core Si waveguides,” Opt. Express18(1), 96–101 (2010). [CrossRef] [PubMed]
  13. S. Ren, T. I. Kamins, and D. A. B. Miller, “Thin dielectric spacer for the monolithic integration of bulk germanium or germanium quantum wells with silicon-on-insulator waveguides,” IEEE Photon. J.3(4), 739–747 (2011). [CrossRef]
  14. A. Nayfeh, C. O. Chui, K. C. Saraswat, and T. Yonehara, “Effects of hydrogen annealing on heteroepitaxial-Ge layers on Si: Surface roughness and electrical quality,” Appl. Phys. Lett.85(14), 2815–2817 (2004). [CrossRef]

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